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Just wondered if anyone has had any luck using any of the virtual machines with 5-level paging.

Bochs doesn't work - modifying CR4.LA57 generates an error that setting that particular bit is not supported.

QEMU supports it, but when I try to view the page table with "info mem" it hangs. Actually, it seems to get stuck in a loop because the CPU load spikes.

I do at least know that 5-level paging is partially working, because the kernel boots part way and encounters a page fault where the faulting instruction is 0xfff0a[...]. That address wouldn't be valid in 4-level paging.

qemu supports 5-level paging correctly (maybe not in the monitor though). Its implementation was contributed by Intel, precedes physical hardware with 5-level paging support and was used as a test bed for the Linux implementation. As for hobby projects: for example, the Limine bootloader can correctly enable and use 5-level paging in qemu.

Korona wrote:qemu supports 5-level paging correctly (maybe not in the monitor though)

It's definitely supporting 5-level paging, or else my code would never get as far as it does.

I do think the problem is in the monitor, though. I stuck in a quick print statement and it appeared to be examining sections of the page table it shouldn't be. It shouldn't be recursing down from entries in the PML5 when P=0, but it looks like it is. At cursory glance, the algorithm for parsing a PML5 table is not just "parse like a PML4 table with an extra level". They're doing it differently, and it may not be working right. I'm going to try modifying it to use the PML4 method, with an extra level, and see if that addresses the issue.

Of course, I can't rule out the possibility that there is a problem with parts of my page tables, but it's hard to verify that when I can't examine them easily.

My bet would be on missing support in the monitor -- for non-x86 archs, "info mem" is also horrible broken so that's no exactly a surprise.

It's there - it specifically checks for LA48 vs. LA57 and recurses the tables differently. It just looks like the LA57 method isn't working right.

It appears "info mem" doesn't work correctly with 5-level paging, even though there's a separate function specifically for LA57 support. I tried two different major versions, including one built from source a few days old, running on different host OS's, with different client OS's, and with 5-level paging in use, it takes longer and outputs nothing.

Oh well. Kind of ironic considering the whole reason I added 5-level paging to my kernel was so that I could test a change I wanted to make to "info mem".