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So ACPI now has the specification in HTML (yay!) and I was looking through it about the definition of the FADT. And it raised a few questions:

1. Does the SCI interrupt get remapped when I remap it when initializing the APIC? For example, on QEMU the interrupt is 9, which is the coprocessor segment overrun exception. I assume it is but I thought I'd ask in case there's some ACPI weirdness going on.
2. Is the SMI command port something I'd write with in/out instructions? And if so, what accesses would I make to that port (e.g.: byte, word, doubleword)?

Ethin wrote:Does the SCI interrupt get remapped when I remap it when initializing the APIC? For example, on QEMU the interrupt is 9, which is the coprocessor segment overrun exception. I assume it is but I thought I'd ask in case there's some ACPI weirdness going on.

Yes. When the hardware has dual 8259 PICs, SCI_INT tells you where the SCI is wired on those, and the MADT tells you if it's wired differently on the APIC. When the hardware doesn't have dual 8259 PICs, SCI_INT tells you the global system interrupt number, which is the same as the APIC input.

Don't confuse global interrupt numbers with CPU interrupt numbers. Interrupt controllers are used to map global interrupts to CPU interrupts, and they shouldn't be configured to use CPU interrupts that are reserved for exceptions.

Ethin wrote:Is the SMI command port something I'd write with in/out instructions? And if so, what accesses would I make to that port (e.g.: byte, word, doubleword)?

Yes. Byte.

Alright, thanks.