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No Base Address Registers!
Posted: Fri Feb 05, 2021 11:44 am
by drnono
I'm scanning the bus for IDE mass storage devices. I can find (some) and get the vendor id's and prog_if etc., but the base address registers all show as zero.
Code: Select all
BAR0_offset = 0x04 << 2;
address = (uint32_t) ( (1<<31) | (bus<<16) | (device<<11) | (func<<8) | BAR0_offset );
outl(PCI_CONFIG_ADDRESS,address);
tmp = inl(PCI_CONFIG_DATA);
ptr=&tmp;
print_dword(ptr,25, 0, 0); // bar0
The mass storage controller is being detected as class and subclass 0x01.
I'm using VMware and bochs alternately, and I noticed that the prog_if registers read 0x80 and 0x8a - corresponding to ISA compatibility modes and not PCI modes.
I tried writing 0x8f (PCI native mode controller) as a dword to offset 0x08 but it had no effect on the BAR registers.
How can I get to read these base address registers?
Re: No Base Address Registers!
Posted: Fri Feb 05, 2021 2:00 pm
by xeyes
What're the vendor and device IDs of this device you are reading from?
If it is the good old PIIX3 (V8086 D7010) common to many VMs the port base is in BAR4 not BAR0.
Otherwise you probably want to consult the documentation for the device you are trying to use.
Re: No Base Address Registers!
Posted: Fri Feb 05, 2021 2:07 pm
by Gigasoft
If you reconfigure the controller, you must allocate addresses and set the BARs yourself.
In VMWare, the mode of operation is always compatibility mode and can't be changed, as indicated by the programming interface byte being 0x80.
BAR4 is for the Bus Master DMA engine.
Re: No Base Address Registers!
Posted: Sat Feb 06, 2021 2:21 pm
by Ankeraout
This Wiki page states that:
Each IDE controller appears as a device on the PCI bus. If the class code is 0x01 (Mass Storage Controller) and the subclass code is 0x1, (IDE) this device is an IDE Device. The IDE device only uses five BARs out of the six
BAR0: Base address of primary channel (I/O space), if it is 0x0 or 0x1, the port is 0x1F0.
BAR1: Base address of primary channel control port (I/O space), if it is 0x0 or 0x1, the port is 0x3F6.
BAR2: Base address of secondary channel (I/O space), if it is 0x0 or 0x1, the port is 0x170.
BAR3: Base address of secondary channel control port, if it is 0x0 or 0x1, the port is 0x376.
BAR4: Bus Master IDE; refers to the base of I/O range consisting of 16 ports. Each 8 ports controls DMA on the primary and secondary channel respectively.
Re: No Base Address Registers!
Posted: Sat Feb 06, 2021 2:45 pm
by Gigasoft
The Wiki page is wrong. The only correct way to determine if a channel is in compatibility mode is by inspecting the Programming Interface register. If it is, the corresponding BARs must be ignored.
Re: No Base Address Registers!
Posted: Sat Feb 06, 2021 4:07 pm
by Octocontrabass
I've updated that section of the wiki with information from the actual PCI IDE specifications. I have to wonder where that nonsense originally came from...
Re: No Base Address Registers!
Posted: Sat Feb 06, 2021 10:13 pm
by nullplan
Octocontrabass wrote:I've updated that section of the wiki with information from the actual PCI IDE specifications. I have to wonder where that nonsense originally came from...
The contended section was added to the page by the page's creator, Mostafazzio, on November 8, 2009. No edit comment there; they didn't seem to be too fond of those. So no clue about their sources.