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Alright, I realize this is a silly sounding question, and I'm ashamed to even ask it, but I googled around for a while and couldn't find any sort of official documentation about the I/O APIC from Intel.

The Intel manual has a nice section about the local APIC, where it lists the registers, but I couldn't find any such section about the I/O APIC.
Did I just glaze right over it without even noticing?
Where did terms like "IOAPICID" and "IOREDTBL" come from in the wiki page for I/O APICs?
Is the MultiProcessor Specification from 1997 all we have?

Try https://pdos.csail.mit.edu/6.828/2014/r ... ioapic.pdf

Thanks.
It seems odd that Intel wouldn't have more information about the I/O APIC in their current manual.
Is I/O APIC somehow considered legacy or deprecated or something like that?

I/O APIC isn't a part of the CPU. It generally is in the chipset. Because the I/O APIC is unrelated to the CPU, they have no need to put it in the manuals. Also, in theory, it is deprecated because we now have MSI and MSI-X, which is must faster. But those only work with PCI devices .

nexos wrote:Because the I/O APIC is unrelated to the CPU, they have no need to put it in the manuals.

Ah, that makes things a good bit clearer.

So if I wanted to use MSI for PCI interrupts, could I get away with just not bothering with the I/O APIC altogether? I'm currently trying to generate and handle timer IRQs from the PIT and it would be super convenient to not have to care about the I/O APIC.

peachsmith wrote:So if I wanted to use MSI for PCI interrupts, could I get away with just not bothering with the I/O APIC altogether?

Yes, as long as you're using PCI devices that support MSI. (All PCIe devices support it.)

Awesome.
I'll just focus on the local APIC when implementing timer IRQs from the PIT then.