check_cs(0x2b): not a valid code segment (0x2b is a TSS)
Posted: Sat Dec 26, 2020 9:14 am
Why can't the interrupt handler iret with this? I thought you can far jump into TSSs.
Having a TSS in ring 3 seems a bit strange. I think you would normally have TSSes in kernel with ring = 0 as the privilege level (RPL field of selector). Also, what DPL does the TSS have?clementttttttttt wrote:Why can't the interrupt handler iret with this? I thought you can far jump into TSSs.
Also, the processor changes the TSS type to busy and if you iret to an TSS I think NT flag must be set and the TSS must be busy. Normal task switching with TSS will use far jmps and TSS RPL & DPL set to 0.
Since it is an interrupt, if interrupts can happen in ring 0, then the TSS must have RPL of 0.