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Hey guys.
I'm developing an OS for 80386 and am currently looking to implement paging. However I want logical addresses to be generated only in Userland (Ring 3) and all addresses in ring 0 to be physical. Is this possible and if yes, how can I do so?
I understand that paging gets enabled upon setting PG in CR0. If I set the bit right before my IRET, then the stack pointer address (esp) used by IRET for retrieving the CS, IP, EFLAGS, ESP, SS etc is also logical right? Any way to make sure logical addressing is used only after IRET completes?

darkknight97 wrote:However I want logical addresses to be generated only in Userland (Ring 3) and all addresses in ring 0 to be physical.

Why?

darkknight97 wrote:Is this possible and if yes, how can I do so?

Sort of. You can use the hardware task switching mechanism to change CR3 when the privilege level changes, so you can have one set of page tables that identity map everything for ring 0, and another set of page tables that provide some other mapping for ring 3.

The end result will be that every system call invalidates the TLB. This doesn't sound like the most efficient way of working.

You must use some really compelling reason for this.