when to reset page table...

[ITchimp]

I am following the james molloy tutorial ... getting to multitasking part...


In the "paging" section of the tutorial, he had code that contracted and enlarge kernel heap that requires the explicit making of the address space .. ie fill in the page directory entry, page table entry and fill in the page frame... but there is no need to reassign the CR3 register to reset the paging circuit...

In the multitasking section of the tutorial, he talks about creating the address space for the newly created stack, but this time he
included the code to reset the CR3 register...

so my question: what is the criteria for resetting the paging circuit for reassigning the CR3 register?

[nullplan]

so my question: what is the criteria for resetting the paging circuit for reassigning the CR3 register?

The criterion is: Do you merely add access, or do you remove/change access? If you add access to a previously unavailable address, you don't need to invalidate the TLB (which is what reloading CR3 does), because at least AMD CPUs are documented to reread the page table in that case, and Intel CPUs might just generate a spurious page fault (that is fixed simply by returning from that interrupt). But if you remove access to an address, or you change where an address is mapped to, or you remove access for user space, or you set a previously writable page to read-only, then you have to invalidate the TLB, because then it is wrong. And one way to do that is to reload CR3. Note that this won't invalidate TLB for pages marked as global, but then, invalidating those is rarely required.

Since invalidating all TLBs is a bit of a performance hit, you usually want to avoid that if possible. So a less scattershot approach is to just use "invlpg" anyway. But if you are replacing large parts of the address space (e.g. when switching processes), then reloading CR3 is still faster than invalidating every single userspace mapping.

[nexos]

That paging code is no good in my opinion. Use this one instead. Note that you should look into recursive paging as well.

[ITchimp]

Can you elaborate a bit on the TLB marked as global, I understand that since all processes share the same kernel
from 0xc00000000 to the end on a 32-bit machine? I don't actually see the page table entry that has a flag named
global? so how do you mark a TLB entry as global?

[Octocontrabass]

I don't actually see the page table entry that has a flag named global?

Where are you looking? You should be able to find it in any recent Intel or AMD manual.

[nullplan]

I don't actually see the page table entry that has a flag named
global? so how do you mark a TLB entry as global?

Intel SDM, Vol. 3A, page 4-10 (which is page 2814 in the collected release of all SDM volumes), says that the G bit is bit 8 in the page table entry. It is only used on the lowest level, and only if CR4.PGE = 1. In PAE paging and 4-level paging, the G bit is also bit 8, but the page table entries are 64-bit entries then.

If you have a manual that does not detail these bits, I strongly suggest updating to the newest Intel SDM or AMD APM, depending on taste. The differences are minor. But Intel does offer a single PDF file with all SDM volumes, so there's that.