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kprintf("Started config of kernel's ATA driver...\n");
reg_config(); // Start ATA driver,
kprintf("Kernel ATA driver configured!\n");
int x = reg_pio_data_in_lba48(0, CMD_READ_SECTORS, 0, 10, 0, 100, (unsigned char *)buffer, 10, 0);
if(x == 0) kprintf("OK data read");
else
{
	kprintf("Error data read\n");
	kprintf("Status register: ");
	kprintf((const char *)reg_cmd_info.st);
	kprintf((const char *)reg_cmd_info.ec);
	kprintf((const char *)reg_cmd_info.er);
}

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int SYSTEM_WAIT_INTR_OR_TIMEOUT(void)
{
    int x = 1000;

    while(ata_int_raised == 0)
    {
        if(x != 5000)
        {
            kwait(x);
            x += 1000;
        }
        else return 1;
    }

    return 0;
}

long SYSTEM_READ_TIMER(void)
{
	return kticks; // Just ticks value incremented by PIT
}

Code: Select all

#define MIN_ATA_DRIVER_VERSION "0H"

//********************************************************************
//
// !!! What parts of MINDRVR do you want in your build?
//
//********************************************************************

#define INCLUDE_ATA_DMA   1   // not zero to include ATA_DMA

#define INCLUDE_ATAPI_PIO 1   // not zero to include ATAPI PIO

#define INCLUDE_ATAPI_DMA 0   // not zero to include ATAPI DMA

//********************************************************************
//
// !!! System specific functions and data you must supply
//
//********************************************************************

// You must supply a function that waits for an interrupt from the
// ATA controller. This function should return 0 when the interrupt
// is received and a non zero value if the interrupt is not received
// within the time out period.

extern int SYSTEM_WAIT_INTR_OR_TIMEOUT( void );

// You must supply a function that returns a system timer value. This
// should be a value that increments at some constant rate.

extern long SYSTEM_READ_TIMER( void );

// This defines the number of system timer ticks per second.

#define SYSTEM_TIMER_TICKS_PER_SECOND  18L

//********************************************************************
//
// !!! ATA controller hardware specific data
//
//********************************************************************

// ATA Command Block base address
// (the address of the ATA Data register)
#define PIO_BASE_ADDR1 ( (unsigned char *) 0x1F0 )

// ATA Control Block base address
// (the address of the ATA DevCtrl
//  and AltStatus registers)
#define PIO_BASE_ADDR2 ( (unsigned char *) 0x3F6 )

// BMIDE base address (address of
// the BMIDE Command register for
// the Primary or Secondary side of
// the PCI ATA controller)
#define PIO_BMIDE_BASE_ADDR ( (unsigned char *) 0x1F7 )

// Size of the ATA Data register - allowed values are 8, 16 and 32
#define PIO_DEFAULT_XFER_WIDTH 16

// Interrupts or polling mode - not zero to use interrrupts
// Note: Interrupt mode is required for DMA
#define INT_DEFAULT_INTERRUPT_MODE 0

// Command time out in seconds
#define TMR_TIME_OUT 20