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After some headbanging and a bit of late googling i discovered that on modern x86 CPUs the RDTSC instruction does not return actual instruction count, and is instead normalized to some system frequency.

This means that as the CPU clock gets changed by nice things like turbo boost, the counter keeps ticking at the same rate.
It no longer measures how many instructions a CPU performed between two invocations, but is now just a clock.

And a clock is not useful when you try to benchmark a bit of code on an x86 tablet that can vary between 1.1GHz and 2.4GHz with no way of nailing it down.

So the question is, is there some new instruction, MSR, or something that holds an actual instruction count?

It sounds like you want RDPMC, with a performance counter configured to count retired instructions.

I haven't used performance counters before so I can't do much besides directing you to the Intel manual, volume 3B chapters 18 and 19.

Yep, that worked. Thanks.

So, the sequence is:
-Write 0xB2 to MSR 0x38D (IA32_FIXED_CTR_CTRL), to enable the instruction counter.
-Set ECX to 0x40000000 (Selects which counter to use)
-RDPMC
-Result in EDX:EAX
To disable counter, write 0 to the same MSR.

The instruction would GPF in userspace by default, you need to set PCE bit in CR4 (bit 8 ) to allow it to be used at lower privilege levels.