#GP on some ISRs, APIC and PIT not sending IRQs

[K3achas]

Hello. I've been working on code to test the speed of the APIC using the PIT. There are several problems I can't figure out. First, when testing my ISRs for the two timers, I get general protection faults on returning from the interrupts. Second, neither timer actually fires any interrupts. Any help on this would be much appreciated.

Link to the relevant file.

[K3achas]

Update: I figured out what was causing the #GPs. I hadn't loaded the right CS. Unfortunately, my code for loading the right CS doesn't work. When trying to load a new code segment for my bootloader, my code produces a #GP fault. Here is a link to the relevant code.

Edit: And i wasn't getting interrupts because I forgot to unmask them .

[nullplan]

Code: Select all

mov [rbx + gdt + 0x8], rax	; code segment 0x8
[...]
cs_swap:push qword 0x10
	lea rax, [rel slb0]
	push rax
	retf

Notice the problem yet? Your code segment is 0x08, but you are trying to enter segment 0x10.

[K3achas]

Thanks for pointing out that flaw. Unfortunately, that did not fix it.

[K3achas]

I managed to solve the code by interrupting to load the right CS instead. Thanks to all who helped. The right code has been uploaded. The rest of this post will be stuff to help people search for the answer.

x86 reload CS. x86_64 reload CS. x86_64 load CS. x86_64 cannot load CS. x86_64 long mode load CS.

[Octocontrabass]

There's nothing wrong with using RETF to change CS, and I'd strongly recommend you change your code back to using RETF for clarity.

The reason it didn't work for you is NASM. When generating 64-bit code, NASM assembles RETF into the 32-bit form instead of the expected 64-bit form. You have to use "RETFQ" to get the expected 64-bit RETF.

(For comparison, YASM will produce the expected 64-bit RETF when generating 64-bit code.)