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Intel's 64 and IA-32 Developers Manual (#325462-043US) denotes on page 2328

LM: IA-32e mode support.
If CPUID.80000001H:EDX.LM [bit 29] = 1, IA32_EFER.LME may be set to 1,
enabling IA-32e paging. (Processors that do not support CPUID function
80000001H do not allow IA32_EFER.LME to be set to 1.)

and on previous page

PAE: physical-address extension.
If CPUID.01H:EDX.PAE [bit 6] = 1, CR4.PAE may be set to 1, enabling PAE
paging (this setting is also required for IA-32e paging).

In my mind, LM should imply PAE but the highlighted text leads me to think that might not be the case.

Could this be possible and if so, on which devices?

No, this is impossible, since enabling PAE is a prerequisite for enabling LM.

nullplan wrote:No, this is impossible, since enabling PAE is a prerequisite for enabling LM.

The diagram on pg 2325 supports exactly that. Suppose I was just reading a little too much into it as I thought, what is the point of overstating the obvious. Then again, if someone didn't read the previous 6 pages up to 4.1.4, then it might not be that obvious.

I think you just misread. The text you quoted said "this is also required...". But it doesn't say what it means with "this": The feature bit or the setting. However, from context and background knowledge it is clear that they must have meant the setting.

The background knowledge in this case is the knowledge of how to enter long mode. Which I never read in the Intel manual, but in AMD's architecture programmer's guide vol 2. (Essentially, you go to long mode by going to non-paged protected mode and enabling PAE-paging while EFER.LME=1. You leave long mode by disabling paging)