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Hello everyone,

my IDE driver works qemu, but on real hardware I don't get an interrupt. The drive is connected via SATA cable and I've set the the SATA Mode in BIOS to "IDE".

I read the PCI configuration space where I found the SATA controller in IDE mode (bus: 0, device: 0x1f, function: 0x2) with following values:
Prog IF has value 0x8F which means "PCI native mode controller, supports both channels switched to ISA compatibility mode, supports bus mastering", so
I changed its value to 0x8A (ISA Compatibility mode controller, supports both channels switched to PCI native mode, supports bus mastering) to enable ISA compatibility mode.

Now, I use these addresses for the driver:
First channel:
cmd: 0x1F0
cnl: 0x3F6
Second channel:
cmd: 0x170
cnl: 0x376

I followed the tutorial on PCI IDE [1] and ATA PIO [2] and found the drive on channel 0, drive 0 as ATA device. When trying to read I wait for BUSY bit to be cleared, set the drive/sector, wait for DRDY bit to be set, then send the command:
Now, I expect the interrupt 14 to happen, but it does not. The nIEN bit is cleared, the error register does not indicate any error, status register has value 0x58, command register also has value 0x58 (the same as in qemu).

Are there any other steps involved that I have missed?

I checked how linux handles this via lspci -v command. There, the sata controller is in PCI native mode (prog-if: 0x8f) and IRQ 19 is used so it seems IOAPIC is used? Do I also have to parse the MADT/APIC to get the mapping and use this instead of switching to PCI compatibility mode and use IRQ 14?

Thanks in advance!


[1] https://wiki.osdev.org/PCI_IDE_Controller
[2] https://wiki.osdev.org/ATA_PIO_Mode

Check the PIC ISR and IRR. Have they both received IRQ14? Are either waiting for you to acknowledge IRQ14 before they can send another IRQ14?

It's also possible the SATA controller supports the legacy IRQs but isn't connected to send them anywhere. You'll need to support the IOAPIC at some point, so now might be a good time to work that out.

I checked IRR and ISR, IRR is sometimes 0x1 (should be the keyboard driver, which is working with IRQs) and ISR is always 0x0.

Then I'll try IOAPIC at this point, thank you.

And just for understanding:
I've read the data sheet of the chipset I'm using (Intel H97), section 5.9 (8259 Programmable Interrupt Controllers (PIC))) mentions the following:

The PCH incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts can include: system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 controller supports eight interrupts, numbered 0–7. Table 5-13 shows how the controllers are connected.

So this means, it is entirely chip dependant if some (legacy) functionality is available (e.g. SATA controller in IDE mode connected to legacy IRQs)?

xvi wrote:I checked IRR and ISR, IRR is sometimes 0x1 (should be the keyboard driver, which is working with IRQs) and ISR is always 0x0.

You're checking both PICs, right?

xvi wrote:So this means, it is entirely chip dependant if some (legacy) functionality is available (e.g. SATA controller in IDE mode connected to legacy IRQs)?

Yes. That datasheet makes it sound like the legacy IDE IRQs are connected, so I'm not sure why it's not working for you, unless the chipset requires some extra configuration to enable it.

You're checking both PICs, right?

Yes. I read the registers as it is shown in the osdev wiki (8259 PIC).

Yes. That datasheet makes it sound like the legacy IDE IRQs are connected, so I'm not sure why it's not working for you, unless the chipset requires some extra configuration to enable it.

So if there is any extra configuration to be done, is there any specific source to read? So far, I have read the data sheet of the chip I'm using, PCI IDE controller specification and the ATA-ATAPI 6 specification. There are some specific mentions regarding legacy IRQs in the PCI IDE specification that I have already tried, but with no effect. I can try that again, maybe I have missed something there.

You could try looking for a specification update for the chipset, but aside from that I don't know of any easily available documentation that would tell you what you need to know.

There's some more information for firmware developers that certainly covers everything you need, but Intel requires a NDA to see any of those documents.

You could try looking for a specification update for the chipset, but aside from that I don't know of any easily available documentation that would tell you what you need to know.

There's some more information for firmware developers that certainly covers everything you need, but Intel requires a NDA to see any of those documents.

Okay, then I'll reread it again and if that does'nt work, I'll try IOAPIC.

Thank you very much for your help!