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Hello, one and all. This is my first post so please go easy on me!

I am trying to implement EHCI in my OS, but I have encounted a bug specefic to one of my computers.

The BAR0 address from the PCI configuration space, leads to what is meant to be the host controller capability registers. On my old computer that I have, this value works and I can access them and further registers for configuration. On my main computer, when reading back the CAPLENGTH and other registers, a value of all 1s is written into all of the memory locations starting at the BAR0 address.

Is there a way to make the PCI device write and use it's host controller registers? The BAR0 address currently resides outside of Physical RAM on the convicted computer and I have tried a few methods of writing to the PCIs configuration space to change it and initialise the device, with no luck.

Edit: The BAR0 is a memory mapped 32 bit address, with bits 0-3 all 0.

Any pointers in the right direction would be appreciated as well as handy hints from previous encounters.

Thanks

What is the actual value of the BAR? Is the device on the PCIe root bus or is it behind a bridge? Did the BIOS configure the bridge? Does the device work on Linux/Windows? Do any crazy BIOS settings regarding EHCI exist? Are you sure the device is actually an EHCI and not a XHCI?

Korona wrote:What is the actual value of the BAR? Is the device on the PCIe root bus or is it behind a bridge? Did the BIOS configure the bridge? Does the device work on Linux/Windows? Do any crazy BIOS settings regarding EHCI exist? Are you sure the device is actually an EHCI and not a XHCI?

1. 0xFED1C400
2. May be behind a bridge.
2. The device works as a custom FAT32 driven flash drive on both Windows and Linux.
4. No the Bios has no handoff/legacy settings.
5. Yes the device is EHCI, having: the correct Classcode, Subclass and Prog IF.

I decided to try and divert my attention to reading from a SATA disk based on a PCI bus, so I got the BAR5 address and found that I am getting the same result from the EHCI bug, all one's get read when reading from the hardware registers.

Is this the case with uncachable memory, that they might be write only, or am I missing something obvious?

This is based on real hardware.

Thanks

Ok, it turns out it was the A20 line that I didn't enable. 3 lines of code (to test it) later and my problem was solved.