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void i8254x_init_card(int i) { // i is an index to an the array of adapters
	pci_register_irq_handler_idx(i8254x_cards[i].pci_idx,i8254x_irq_handler);
	pci_write_config_dword_idx(i8254x_cards[i].pci_idx,PCI_CONFIG_COMMAND,(pci_read_config_dword_idx(i8254x_cards[i].pci_idx,PCI_CONFIG_COMMAND) | (1<<2))); // enable pci busmastering, if it helps
	i8254x_mmio_write32(i,I8254X_REG_IMS,0x1f6dc); // set interrupt mask; should be 0x1ffff, 0x17fff or maybe 0x1f6dc?
	i8254x_init_mta(i);  // init multicast table
	i8254x_set_link_up(i); // set CTRL.SLU, CTRL.ASDE and clear CTRL.LRST
	i8254x_init_rx(i); // init receive
	i8254x_init_tx(i); // init transmit
	}

void i8254x_init_rx(int i) {
	u8 mac[6];

	i8254x_cards[i].rx_descs = pfa_alloc(I8254X_RXDESC_PGCOUNT); // allocate memory (in pages) for rx descriptors
	for (int j=0;j<(256*I8254X_RXDESC_PGCOUNT);j++) {  // iterate through each rx descriptor
		i8254x_cards[i].rx_descs[i].address = (u32)PG_V2P(pfa_alloc(2)); // allocate 8192 byte packet, and write physical address
		i8254x_cards[i].rx_descs[i].status = 0; // clear status so the controller knows it can be used
		}
	i8254x_read_mac(i, &mac); // read mac from eeprom
	i8254x_mmio_write32(i, I8254X_REG_RAL + (i*8), ((mac[3]<<24) | (mac[2]<<16) | (mac[1]<<8) | mac[0])); // set up MAC filter
	i8254x_mmio_write32(i, I8254X_REG_RAH + (i*8), (0x80000000 | (mac[5]<<8) | mac[4]));
	i8254x_mmio_write32(i, I8254X_REG_RDBAH, 0); // no 64 bit here
	i8254x_mmio_write32(i, I8254X_REG_RDBAL, (u32) PG_V2P(i8254x_cards[i].rx_descs)); // set pointer to descriptor array
	i8254x_mmio_write32(i, I8254X_REG_RDLEN, I8254X_RXDESC_COUNT * 16); //I8254X_RXDESC_PGCOUNT * I8254X_RXDESC_PER_PAGE * 16
	i8254x_mmio_write32(i, I8254X_REG_RDH, 0); // set head to 0, as the manual says
	i8254x_mmio_write32(i, I8254X_REG_RDT, I8254X_RXDESC_COUNT); // set tail to the index after the last descriptor, as the manual says
	i8254x_cards[i].rx_tail = 0; // set our tail to 0, because that works
	i8254x_mmio_write32(i, I8254X_REG_RCTL, (I8254X_RCTL_SBP | I8254X_RCTL_UPE | I8254X_RCTL_MPE | I8254X_RDMTS_HALF | I8254X_RCTL_SECRC | I8254X_RCTL_LPE | I8254X_RCTL_BAM | I8254X_RCTL_BSIZE_8192)); // set the receive control register (promisc, 8K pkt size)
	}

int i8254x_irq_handler(u8 irq) {
	int status = 0;

	for (int i=0; i<i8254x_count; i++) {
		if (i8254x_cards[i].pci_irq == irq) status = i8254x_irq_handler2(i);
		if (status != 0) break;
		}
	return status;
	}

int i8254x_irq_handler2(int idx) {
	u32 icr = i8254x_mmio_read32(idx,I8254X_REG_ICR); // read interrupt code
	u32 sicr = icr; // save icr for later

	if (!icr) return 0; // return 0 (irq not processed) if no interrupt flags set
	if (icr & I8254X_ICR_LSC) { // link status change
		printf("i8254x_irq_handler2: link status change\n");
		icr &= ~(I8254X_ICR_LSC); // clear bit
		i8254x_enable_rx(idx);
		}
	if ((icr & I8254X_ICR_RXT0) || (icr & I8254X_ICR_RXDMT0)) { // packet rx'd
		icr &= ~(I8254X_ICR_RXT0 | I8254X_ICR_RXDMT0); // clear bits
		i8254x_rx_poll(idx);
		}
	printf("i8254x_irq_handler2: rxfifo status: h=%u t=%u(%u)\n",i8254x_mmio_read32(idx,I8254X_REG_RDH),i8254x_mmio_read32(idx,I8254X_REG_RDT),i8254x_cards[idx].rx_tail);
	printf("i8254x_irq_handler2: %u (%u)\n",(unsigned int)icr,(unsigned int)sicr);
	i8254x_mmio_read32(idx,I8254X_REG_ICR); // clear interrupts; is this necessary?
	return 1; // tell caller the irq was handled
	}

void i8254x_enable_rx(int i) {
	i8254x_mmio_write32(i, I8254X_REG_RCTL, i8254x_mmio_read32(i, I8254X_REG_RCTL) | (I8254X_RCTL_EN));
	}

void i8254x_rx_poll(int idx) {
	printf("i8254x_rx_poll: status=%u\n",i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].status);
	while ((i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].status & I8254X_RXDSTS_DD)) { // while the tail packet has STATUS.DD set
		u16 pkt_len = i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].length; // packet length
		bool dropflag = FALSE;

		if (pkt_len < 60) { // small packet
			//printf("i8254x_rx_poll: small packet, %u bytes; dropping\n",pkt_len);
			printf("d");
			dropflag = TRUE;
			}
		if (!(i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].status & I8254X_RXDSTS_EOP)) { // eop not set
			//printf("i8254x_rx_poll: eop not set? dropping\n");
			printf("D");
			dropflag = TRUE;
			}
		if (i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].errors) { // packet had errors
			printf("i8254x_rx_poll: packet had errors; dropping\n");
			dropflag = TRUE;
			}
		if (!dropflag) { // packet has no reason to be dropped
			printf("i8254x_rx_poll: good packet # %u, %u bytes\n",i8254x_cards[idx].rx_count,pkt_len);
			i8254x_cards[idx].rx_count++;
			}
		i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].status = 0; // inform hardware descriptor is ready to use
		i8254x_cards[idx].rx_tail = (i8254x_cards[idx].rx_tail + 1) % I8254X_RXDESC_COUNT; // set tail to next descriptor, wrap if necessary
		i8254x_mmio_write32(idx, I8254X_REG_RDT, i8254x_cards[idx].rx_tail); // inform hardware of new tail
		i8254x_mmio_read32(idx, I8254X_REG_ICR); // clear interrupts?
		}
	}

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i8254x_cards[i].rx_descs[i].address = (u32)PG_V2P(pfa_alloc(1)); // the index for rx_descs should have been j, not i.

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#define PG_SIZE 4096

#define I8254X_RXDESC_PGCOUNT 1
#define I8254X_RXDESC_PER_PAGE (PG_SIZE / 16) // 256
#define I8254X_RXDESC_COUNT (I8254X_RXDESC_PGCOUNT * I8254X_RXDESC_PER_PAGE) // 256

#define I8254X_RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))  // (1 << 25) = BSEX
#define I8254X_RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))

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#define I8254X_REG_RDBAL 0x2800
#define I8254X_REG_RDBAH 0x2804
#define I8254X_REG_RDLEN 0x2808
#define I8254X_REG_RDH 0x2810
#define I8254X_REG_RDT 0x2818

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RDH = 0;
RDT = I8254X_RXDESC_COUNT;
rx_tail = 0;

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RDH = 0;
rx_tail = RDT = I8254X_RXDESC_COUNT - 1;

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void i8254x_rx_poll(int idx) {	
	while (i8254x_cards[idx].rx_descs[I8254X_INC_RDT(i8254x_cards[idx].rx_tail)].status & I8254X_RXDSTS_DD) { // if dd set in next descriptor from rx_tail
		i8254x_cards[idx].rx_tail = (i8254x_cards[idx].rx_tail + 1) % I8254X_RXDESC_COUNT;

		u16 pkt_len = i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].length; // packet length
		bool dropflag = FALSE;

		if (pkt_len < 60) { // small packet
			printf("d");
			dropflag = TRUE;
			}
		if (!(i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].status & I8254X_RXDSTS_EOP)) { // eop not set
			printf("D");
			dropflag = TRUE;
			}
		if (i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].errors) { // packet had errors
			printf("i8254x_rx_poll: packet had errors; dropping\n");
			dropflag = TRUE;
			}
		if (!dropflag) { // packet has no reason to be dropped
			printf("i8254x_rx_poll: good packet # %u, %u bytes\n",i8254x_cards[idx].rx_count,pkt_len);
			i8254x_cards[idx].rx_count++;
			}
		i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].status = 0;
		i8254x_cards[idx].rx_descs[i8254x_cards[idx].rx_tail].errors = 0;
		i8254x_mmio_write32(idx, I8254X_REG_RDT, i8254x_cards[idx].rx_tail);
		}
	}

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// upon enter, RDT == rx_tail.
tail = (rx_tail + 1) mod count;
while (desc[tail].status.DD) {
   // work on desc[tail].
   // clear desc[tail].

   // advance the RDT to release the previous
   // desc for use by hw. 
   rx_tail = RDT = tail;
   
   // work on the next desc.
   tail = (tail + 1) mod count;
}