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I have a simple question what is the problem that the CPU have when it going to the ring 0 and it needs tss?
Another similar question, I have 6 descriptions on gdt:
1) the null description on relative address 0x00
2) the ring 0 code description on relative address 0x08
3) the ring 0 data description on relative address 0x10
4) the ring 3 code description on relative address 0x18
5) the ring 3 data description on relative address 0x20
6) the tss description on relative address 0x28
so on kernel mode I am setting the cs to 0x08 and the ds,es,fs,gs,ss to 0x10
but on user mode I am not setting the cs to 0x18 but the cs to 0x1B (0x18+0x03 (for ring 3)) but the gdt says that when the cs points the 4nd discription we are on ring 3 why to say it 2 times, the CPU cannot understand this with the first?
Also on qemu when I am on user mode it says that the segment registers is on ring 3 but the eflags are saying that we are on ring 0. Maybe I need to do something and for that?

The TSS is needed to get kernel stacks on ring transitions (from less privileged rings to more privileged ones). It can also be used for hardware task switching which might have been a good idea in the 1980s. Hardware task switching is not available on x86_64.

The privilege check on data segments is required in segmented memory models, to prevent ring 3 from accessing memory segments that are owned by ring 0. It would not be required if x86 only supported a flat memory model.

EFLAGS does not hold the CPL. Do you mean the IOPL?

Also relevant for this topic, and something that might cause confusion is that there's three different things:
RPL - Requested Privilege Level
CPL - Current Privilege Level
DPL - Descriptor Privilege Level

You may want to look those up in Intels manuals.