PLL: cpu frequencies and prescalers.

[JulienDarc]

Hi, sorry if it is a stupid question,

While creating the boot configuration (CCU registers) for a Allwinner H3 board, relying on a Cortex a7 quad, came the question of the cpu frequency scale.

The reference clock frequency is 24MHz.

u-boot has the following code

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static struct {
    u32 pll1_cfg;
    unsigned int freq;
} pll1_para[] = {
    /* This array must be ordered by frequency. */
    { PLL1_CFG(31, 1, 0, 0), 1488000000},
    { PLL1_CFG(30, 1, 0, 0), 1440000000},
    { PLL1_CFG(29, 1, 0, 0), 1392000000},
    { PLL1_CFG(28, 1, 0, 0), 1344000000},
    { PLL1_CFG(27, 1, 0, 0), 1296000000},
    { PLL1_CFG(26, 1, 0, 0), 1248000000},
    { PLL1_CFG(25, 1, 0, 0), 1200000000},
    { PLL1_CFG(24, 1, 0, 0), 1152000000},
    { PLL1_CFG(23, 1, 0, 0), 1104000000},
    { PLL1_CFG(22, 1, 0, 0), 1056000000},
    { PLL1_CFG(21, 1, 0, 0), 1008000000},
    { PLL1_CFG(20, 1, 0, 0), 960000000 },
    { PLL1_CFG(19, 1, 0, 0), 912000000 },
    { PLL1_CFG(16, 1, 0, 0), 768000000 },
    /* Final catchall entry 384MHz*/
    { PLL1_CFG(16, 0, 0, 0), 0 },

};

We can see that we have a lot of working values for our cpu freq.

PLL for the CPU is given as:

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(24MHz * N * K) / (M * P) 

If I want a cpu running at 960MHz (severe downclock for power saving reasons), I can use

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(24 * 20 * 2) / (1 * 1) = 960

or

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N * (24 << K) = 20 * (24 << 1) = 960.

NOW, with 0<= N <=31 and 0<= K <= 4 (legal values according to the reference manual), I could also have

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(24 * 10 * 4) / (1 * 1) = 960

or

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10 *(24<<2) =960 

Can someone tell me the difference between thos values at the cpu/board level

I mean, we get the same frequency result, but with different clock and prescalers. Any difference at the consumption level? Will it catch me later?

Thanks

[JulienDarc]

(Does my question make sense?)

[zaval]

it makes sense to only those who has been digging into Allwinner's manuals deeply. Seems there is not much like those over there. It's a very SoC specific question. There are nuances that may have impact similar to that you mentioned or another. But again, telling about how it is on Ingenic's SoC, will give you nothing. Just like for me staring at your excerpts pulled off from the Allwinner's manual. Read it carefully, compare what uboot does (it's not brilliant, but hey, at least it works), that's all. You might yet ask Allwinner. Occasioanally they may answer.

On Ingenic SoC the output frequency of a PLL is defined by formula - Fout = Fin * NF / NR / NO, where NF, NR and NO (multiplyer and dividers) are set by you, but there are limits in which for example Fin/NR (called Fref) should fit. And also VCO = Fref * NF could not be changed more than 20% without loss of stability. So basically you would want to not touch it at all after initialization and make frequency change on CPU etc through their dividers. Additionally you might see, that for some not explained reason both multiplier and one of the dividers are set twice as minimum needed, giving the same result, but inducing a suspect, this is needed for some very PLL specific need.
See, this is kind of about the same, but it's obvious, it's very board specific.
Good luck.

If I want a cpu running at 960MHz (severe downclock for power saving reasons)

it's not as "severe" in fact. I run my FW on 400MHz where the normal freq is 1200 MHz.
And finally failing to figure out what is a "better" way to establish it, you just choose one working. it's not going to blow up or explode. hopefully. your uncertainty is exaggerated. but this is a good thing in this field. i think.)

[JulienDarc]

you are right, it is very specific.

I will ask Allwinner and some community around it.

Anyway, thanks zaval for your answer