[SOLVED] BCM2835 MMU setup
Posted: Wed Jun 07, 2017 8:43 am
Hi guys,
I'm working with a Raspberry Pi Zero (BCM2835) and are currently trying to setup the MMU.
I have tried working with the MMU on a Odroid-C1 with great success.
However, that was a newer architecture (v7 vs v6) and I cannot copy my work entirely from there.
I would appreciate if I could get some help from someone who has worked with the Pi Zero.
Here is my current setup, which halts the system (an exception I assume). It works with the simple 1 MB section mapping:
First, I set the TLB address to 0x10000, where I have 4KB available for the table.
Next, I map the entire table PA = VA as sections with full privileged access and strong order.
Thus, the table content looks like this:
Next, I enable the MMU with the following procedure:
I know it dies right after. I have tried to turn off the led on the board right after saving the register but it never runs.
If anyone has suggestions to make it work, I would be very happy as I can move on with my little kernel
Best regards,
Simon
I'm working with a Raspberry Pi Zero (BCM2835) and are currently trying to setup the MMU.
I have tried working with the MMU on a Odroid-C1 with great success.
However, that was a newer architecture (v7 vs v6) and I cannot copy my work entirely from there.
I would appreciate if I could get some help from someone who has worked with the Pi Zero.
Here is my current setup, which halts the system (an exception I assume). It works with the simple 1 MB section mapping:
First, I set the TLB address to 0x10000, where I have 4KB available for the table.
Code: Select all
MCR P15, 0, R0, C2, C0, 0
Thus, the table content looks like this:
Code: Select all
00000410
00100410
00200410
00300410
00400410
00500410
...
Code: Select all
# Invalidate cache, tlb and DSB.
MOV R0, #0
MCR P15, 0, R0, C7, C7, 0
MCR P15, 0, R0, C8, C7, 0
MCR P15, 0, R0, C7, C10, 4
# Set domain access.
MOV R0, #0xFFFFFFFF
MCR P15, 0, R0, C3, C0, 0
# Setup MMU.
MRC P15, 0, R0, C1, C0, 0
# Enable MMU.
ORR R0, R0, #0x1
# Disable caching.
BIC R0, R0, #(1 << 2)
BIC R0, R0, #(1 << 12)
# Enables subpage.
ORR R0, R0, #(1 << 23)
# Enables TEX-mapping.
ORR R0, R0, #(1 << 28)
MCR P15, 0, R0, C1, C0, 0 <-- This is where it dies.
If anyone has suggestions to make it work, I would be very happy as I can move on with my little kernel
Best regards,
Simon