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Hi all.

I'm just setting up a 64 bit test in assembler so setting up the translation tables. I'm setting as 1GB tables and had a question on the structure. I've seen a few examples where say their PML4E table is at address 1000 and the PDPE is at 2000 etc. In the PML4E table they are setting the pointer to 2003 hence 2000 with two bits set for the switches. In the AMD docs, it shows the first 8 bits as switches and then 4 bits ignored so the address starts at bit 12. What I can't relate to is how the address they show is correct?

Bipman

You're confusing bits and bytes. The difference between 0x2000 and 0x2003 is 2 bytes, not 2 bits

Sorry I didn't mention is was ox2003 i.e. hex. Isn't ox2000 + 11b = ox2003? Anyway, what I am trying to say (I think) is do the first 12 bits of the field that make up the address also include the flags?

Bipman

Bipman wrote:Sorry I didn't mention is was ox2003 i.e. hex. Isn't ox2000 + 11b = ox2003? Anyway, what I am trying to say (I think) is do the first 12 bits of the field that make up the address also include the flags?

Bipman

yes

basically, since the address must be aligned on a 4K boundary, the lower 12 bits of the address will always be 0, therefore, the CPU ignores those bits (assumes they are all 0) and those bits can then be re-used for various flags -- all versions of x86 paging do this

Excellent thanks Just what I needed to know.

Bipman