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Hello guys and girls,

As I read the last thread about paging, a question arises in my mind:
What happens, if you have paging with two pages not mapped to sequential physical memory, and then make one instruction that accesses both pages?

An Example:
Lets assume we have two 4kb-pages. In virtual memory the first page is from 0 to 0xFFF and the second page goes from 0x1000 to 0x1FFF.
But they are mapped not sequential. Lets assume the first page to map to address 0 and the second page to 0x4000.
What happens, if I make a dword (4 byte) access on virtual address 0xFFE? Will the MMU recognize, she has to split the access into two accesses - one word (2 byte) at physical 0xFFE and one word at physical 0x4000? Or will it access the wrong memory from 0xFFE to 0x1001? Will there be a GPF?

Best regards
Sebi

Page translation must be (mostly) transparent or it would be problematic to use. The answer is that the CPU will figure it out for you.

However, at some point intel said that the TSS must lie in physically contiguous memory when page translation is enabled. They hadn't had such a limitation documented in their 80386 and 80486 documentation. Make of it what you will.

To answer the question: there should not be a GPF. There probably will be a page fault. There may also be an alignment check fault if you've enabled that (if you have, you should get that immediately prior to the page fault, meaning you could potentially fix the issue in the alignment check handler).

Thank you! I think I will just try it.