OSDev.org

Posted: **Wed Feb 01, 2017 4:31 am**

I'm currently trying to get the PIT timer to work. My problem however is that I am not receiving any interrupts generated by the timer.
I'm using the I/O APIC to map the IRQs. I know that the I/O APIC code is working properly, because other irqs get mapped correctly. The RTC timer interrupts just fine and keyboard interrupts work too.

What I'm currently doing is the following:
-Map an interrupthandler to interrupt 34 (Which is not yet used)
-Map IRQ 0 to interrupt 34 with the I/O APIC
-Enable channel 0 of the pittimer with a divider value of 11931 to get roughly 100 hz.

The code I'm using to enable the PIT timer:

Code: Select all

uint16_t divisor = 11931;
outb(0x43, 0x36);
outb(0x40, divisor & 0xff);
outb(0x40, (divisor >> 8) & 0xff);

I have the feeling that I'm missing something trivial since the interrupt handling works, and initializing the PIT itself shouldn't be too hard.

Anyone any hints on what might be going wrong here?

Posted: **Wed Feb 01, 2017 6:13 am**

I actually solved it. Apparantly PIT timer interrupts are IRQ2 on the I/O APIC instead of IRQ0. I found this information in the wiki at the HPET topic, section "Legacy Replacement Mapping".

Maybe this should be added to the PIT timer page as well?

Posted: **Wed Feb 01, 2017 10:31 am**

The IRQ override from IRQ0 to IRQ2 is in the ACPI's MADT block.

If you are going to use the IOAPIC, you need to parse the ACPI and the MADT to get these overrides as well as get the base address of the IOAPIC.

i.e.: You should not assume 0xFEC00000.

Posted: **Wed Feb 01, 2017 11:31 am**

D'oh. I'm already getting the IOAPIC address from the MADT table. I completely forgot about the ISO entries in the table.

I was so naive to assume that since the HPET mentioned IRQ2 on IOAPIC, that this was always the case. Thank you for the help!

Posted: **Wed Feb 01, 2017 2:03 pm**

Actually, I tried implement the interrupt source override, however qemu doesn't have such entries, eventhough irq0 is rerouted to irq2. Is this a known bug in qemu?

Posted: **Wed Feb 01, 2017 4:37 pm**

QEMU does emulate the overrides, at least the version I am using.

https://qemu.weilnetz.de/

Ben
http://www.fysnet.net/the_universal_serial_bus.htm

Posted: **Thu Feb 02, 2017 6:53 am**

I'm stupid. Turns out that qemu indeed does have the entries. I forgot to remove a break in my loop going over all the table entries. As soon as it found the first IO APIC it stopped searching.

Thank you for all the help!

OSDev.org

[SOLVED] PIT in combination with IO APIC

[SOLVED] PIT in combination with IO APIC

Re: PIT in combination with IO APIC

Re: [Solved] PIT in combination with IO APIC

Re: [Solved] PIT in combination with IO APIC

Re: PIT in combination with IO APIC

Re: PIT in combination with IO APIC

Re: PIT in combination with IO APIC