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The implementation of this bit is dependent upon the value of the CAP.SAM bit.
If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'.
If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'.

if(pci_info->class.sub_class == 6) //AHCI
{
	printf("Device is AHCI ready!\n");
	
	abar = (HBA_MEM*)(pci_info->address5 & 0xFFFFE000);
	malloc_mark_used_adr((void*)abar);
	
	//Needed to be set for a full reset
	abar->ghc |= 0x80000000;

	Sleep(100);

	//Resetting HBA
	abar->ghc |= 1;
	while(abar->ghc & 1)
		Sleep(10);
	
	Sleep(100);
	
	//Enable AHCI if not enabled yet
	if (!(abar->ghc & 0x80000000))
		abar->ghc |= 0x80000000;
	
	int i;
	for(i = 0; i < 32; i++)
	{
		//Check for drive status
		if(!(abar->pi & (1 << i)))
			continue;
		if((abar->ports[i].ssts & 0x0F) != HBA_PORT_DET_PRESENT || ((abar->ports[i].ssts >> 8) & 0x0F) != HBA_PORT_IPM_ACTIVE)
			continue;
		
		port_rebase(&abar->ports[i], i);
		
		malloc_mark_used_adr(*(void**)&abar->ports[i]);
		
		ahci_devices[i].available = true;
		ahci_devices[i].type = abar->ports[i].sig;
		ahci_devices[i].has_data = false;
		
		device_count++;
	}
}

SpyderTL wrote:Complete shot in the dark here, but did you check the BIOS configuration to make sure it wasn't in IDE compatibility mode?

SpyderTL wrote:Have you tried booting Linux, and does it seem to have any problems with that AHCI controller?

Exactly how old is that machine?

Kazinsal wrote:Perhaps the BIOS isn't releasing control of the HBA. Are you properly handling BIOS/OS Handoff Control (HBA memory offset 0x28)?

printf("Handoff: %X\n", abar->cap2 & 1);
		
abar->bohc |= 2;
		
while(!(abar->bohc & 2) || (abar->bohc & 1))
	Sleep(10);
		
printf("Got access to HBA!\n");

BenLunt wrote:Since the HBA (AHCI controller card) will have an optional ROM BIOS present, it most likely has already reset the HBA for you. It knows exactly how to do it, so I would allow it to. Therefore, skip the HBA reset until you actually need it.

However, I would do a Port Reset on each implemented port causing a COMRESET to be sent.
Write a 1 to PxSCTL.DET, wait a minimum of 1 mS, then clear PxSCTL.DET. Then wait for (with timeout) PxSSTS.DET == 3.

Also, within your code, you do

Code: Select all

while(abar->ghc & 1)
      Sleep(10);

Depending on the compiler and its options, the compiler could completely skip that whole block of code since it can't see any reason abar->ghc would ever change. Is abar set as volatile?

I suggest that you create two functions, one to read a dword from the controller and one to write a dword to the controller.

The compiler might change the read of 'abar->ghc' above to a byte read, where as the HBA might not like that byte read.

Ben
http://www.fysnet.net/media_storage_devices.htm

//Port reset
abar->ports[i].cmd &= ~HBA_PxCMD_ST;

while(abar->ports[i].cmd & HBA_PxCMD_CR)
	Sleep(10);

Sleep(1000);

uint32_t val = (abar->ports[i].sctl & 0xFFFFFFF0) | 1;
abar->ports[i].sctl = val; 

Sleep(1000);

abar->ports[i].sctl &= 0xFFFFFFF0;

while((abar->ports[i].sctl & 0xF) != 3)
{
	printf("sctl: %X\n", (abar->ports[i].sctl & 0xF));
	Sleep(1000);
}

Sleep(1000);

abar->ports[i].serr = 0xFFFFFFFF;

SpyderTL wrote:The staggered spin up flag isn't mentioned on the AHCI wiki page. If you feel like you understand it well enough, can you add a quick section about what it is, and how it affects your driver code?

Thanks.

During initial system power-on in a system that supports staggered spin-up, software needs to spin up
each attached device. In addition, when the system transitions from the S3 or greater system power
management state back to S0, the attached drives will also need to be spun up. In order to spin up the
devices attached to the HBA, software should perform the procedure outlined in section 10.1.1 for
staggered spin-up.

Power On Device (POD): This bit is read/write for HBAs that support cold presence
detection on this port as indicated by PxCMD.CPD set to ‘1’. This bit is read only ‘1’ for
HBAs that do not support cold presence detect. When set, the HBA sets the state of a
pin on the HBA to ‘1’ so that it may be used to provide power to a cold-presence
detectable port.