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I have a few questions based on this bit in the wiki:

Note that interrupts are handled by priority level: 0, 1, 2, 8, 9, 10, 11, 12, 13, 14, 15, 3, 4, 5, 6, 7. So, if IRQ 8 and IRQ 3 come in simultaneously, IRQ 8 is sent to the CPU. When the CPU finishes handling the interrupt, it tells the PIC that it's OK to resume sending interrupts

So if I press a key (IRQ 1) at the same time the PIT (IRQ 0) goes off, will my keypress be ignored? or will it just be sent to the CPU after the PIT interrupt is handled?
And what if an IRQ 0 fires while an IRQ 1 is in the process of being handled (IRQ 1 handler called, but no EOI yet)? I can't imagine it would interrupt the interrupt handler, but that would mean a higher priority IRQ has to wait for a lower one to finish...
And what if the PIT is set to a really high frequecy, and a stupid OS developer made an interrupt handler for IRQ 1 that takes multiple PIT ticks to finish? Would the CPU receive only one IRQ 0? or would it receive multiple IRQ 0s back-to-back? or just none at all?

I have not studied nor researched the PIC as well as I have other things, so my comments may not be as accurate as I wish they were, but here goes.

The PIC will "save" the other interrupt until the first one is done, then it will fire the other interrupt. All interrupts are saved as long as you acknowledge the first one.

If two interrupts of the same number fire before you acknowledge the first one, the second one is lost.
If two interrupts of a different number fire before you acknowledge the first on, the second one is saved.

Again, I haven't researched the PIC near as much as, say the USB (smile), so let someone else verify this for you.

Thanks,
Ben

sleephacker wrote:So if I press a key (IRQ 1) at the same time the PIT (IRQ 0) goes off, will my keypress be ignored? or will it just be sent to the CPU after the PIT interrupt is handled?

The latter.

sleephacker wrote:And what if an IRQ 0 fires while an IRQ 1 is in the process of being handled (IRQ 1 handler called, but no EOI yet)? I can't imagine it would interrupt the interrupt handler, but that would mean a higher priority IRQ has to wait for a lower one to finish...

There are two possibilities: (1) you allow interrupts during your interrupt handler, and the higher-priority interrupt interrupts the lower-priority interrupt, or (2) you don't allow interrupts during your interrupt handler, and the higher-priority interrupt has to wait for the lower-priority interrupt to finish.

If you do allow interrupts in your interrupt handler, you should disable them before the EOI so you aren't interrupted by a lower-priority interrupt.

sleephacker wrote:And what if the PIT is set to a really high frequecy, and a stupid OS developer made an interrupt handler for IRQ 1 that takes multiple PIT ticks to finish? Would the CPU receive only one IRQ 0? or would it receive multiple IRQ 0s back-to-back? or just none at all?

If your IRQ1 handler doesn't allow IRQ0 to interrupt it, you'll receive a single IRQ0 afterwards.

Alright, I think I get it now, thanks for the explanations!