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paging in realmode
Posted: Sun Dec 20, 2015 12:51 pm
by Techel
Do I really have to switch to P-Mode and use VM8086 to utilize Paging in Real-Mode? Or are there other possibilities?
Re: paging in realmode
Posted: Sun Dec 20, 2015 1:18 pm
by Roman
Intel wrote:Paging (bit 31 of CR0) — Enables paging when set; disables paging when clear. When paging is disabled, all linear addresses are treated as physical addresses. The PG flag has no effect if the PE flag (bit 0 of register CR0) is not also set; setting the PG flag when the PE flag is clear causes a general-protection exception (#GP). See also: Chapter 4, “Paging.”
Re: paging in realmode
Posted: Sun Dec 20, 2015 1:38 pm
by Techel
I know this and thought of 16 bit P-Mode but that would not work, so I only have the possibility I mentioned above, right?
Re: paging in realmode
Posted: Sun Dec 20, 2015 3:29 pm
by Techel
Another question: When changing a segment register in realmode the base field in the shadow descriptor register is updated accordingly (ie. multiplying the value by 16 and storing it). Does this only affect the lower 16 bit (as the base field is 32 bit in size) or are the upper bits set to 0?
Re: paging in realmode
Posted: Sun Dec 20, 2015 3:46 pm
by Kevin
Roflo wrote:Do I really have to switch to P-Mode and use VM8086 to utilize Paging in Real-Mode? Or are there other possibilities?
In theory, you could switch to PM and use VMX/SVM instead of VM86. I doubt this is going to make it any easier, though, while restricting your code to relatively new hardware. I imagine there might be obscure use cases for doing something like this with a LM kernel, but not when you explicitly switch to PM just in order to get paging.
Re: paging in realmode
Posted: Sun Dec 20, 2015 5:51 pm
by alexfru
Roflo wrote:Another question: When changing a segment register in realmode the base field in the shadow descriptor register is updated accordingly (ie. multiplying the value by 16 and storing it). Does this only affect the lower 16 bit (as the base field is 32 bit in size) or are the upper bits set to 0?
You're still limited to a 20-bit base address (do the math: 16-bit segment selector shifted left 4 positions), irrespective of the details of hardware implementation. About the only thing you can do with memory addressing in real mode is extending the segment limit beyond 65535 bytes (look up Big Real Mode / Unreal Mode).
Re: paging in realmode
Posted: Sun Dec 20, 2015 6:03 pm
by alexfru
Kevin wrote:In theory, you could switch to PM and use VMX/SVM instead of VM86. I doubt this is going to make it any easier, though, while restricting your code to relatively new hardware. I imagine there might be obscure use cases for doing something like this with a LM kernel, but not when you explicitly switch to PM just in order to get paging.
Yep, VMX/SVM comes with lots of flexibility and complexity (not to mention the obvious necessity of having to implement separate versions (or abstraction layers) for both as VMX and SVM aren't compatible). Writing a lot of boilerplate code and debugging the whole thing isn't going to be fun. And it's much less known than virtual 8086 mode (few people have on-hand knowledge (I myself didn't study in depth everything in VMX/SVM while working on Hyper-V)), meaning there's going to be little help on this or another forum. Reading the dull manuals and experimenting won't be cheap or pleasant.