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Hi,

on one PCI bus, all devices share the A,B,C,D int pins right?
On bus0, I have 3 devices that uses PinA:
00:01:03 8086/7113
00:03:00 10EC/8139
00:04:00 10EC/8139

but then, the MP tables tell me that
00:01 PINA -> ioapic index 09
00:03 PINA -> ioapic index 0B
00:04 PINA -> ioapic index 0B
How can the same PINA be connected to ioapic pin 0x9 and 0xB?
Does it mean that when pci bus0 PINA gets pulled low, ioapic int 0x9 and 0xb will be fired?
or does it have something to do with the line shuffling on the board, where PINA for ioapic pin9 is not really PINA but one of the 3 others? Am I making any sense? this is confusing.

Thanks.

Hi,

It's called "barber pole", and it goes sort of like this:
Mostly "INTA" on the first PCI slot is connected to "INTB" on the second slot and "INTC" on the third slot. With this arrangement, all devices can use "INTA" (at their slot) and they get spread across all PCI interrupt lines (at the PCI host controller) evenly.


Cheers,

Brendan

That's what I thought. So the pin number reported by the MP tables is from the device's point of view and NOT the bus point of view then.

So you are confirming that, as per my example, when device 00:01 will trigger an interrupt, only IOAPIC lin 9 will be asserted and not 0x0b. Right?

Hi,

xmm15 wrote:So you are confirming that, as per my example, when device 00:01 will trigger an interrupt, only IOAPIC lin 9 will be asserted and not 0x0b. Right?

Yes


Cheers,

Brendan