OSDev.org

Hello,

My current goal is to reduce the code size of my os.

In ring0, is the IOPL always checked too in the TSS?

Which would incur that I cannot do without a TSS, even almost empty, and even if its location in memory causes cache misses (I can locate it elsewhere but..).

Thanks

Julien

IOPL is part of eflags, so no, it's obviously not checked in the TSS. The I/O bitmap is in the TSS and it's probably not accessed if IOPL already gives sufficient privileges.

However, the Intel manual states cleary that "when operating in protected mode, a TSS and TSS descriptor must be created for at least one task, and the segment selector for the TSS must be loaded into the task register (using the LTR instruction).". So yes, not having a TSS is a mistake.

If you plan on using multiple rings you will need at least a single TSS.

If you're currently executing in ring3 and you get an interrupt causing ring3->ring0 transition then the TSS is used to set ring0 SS:ESP. Other than that I'm not sure if you need one. I was thinking of it myself as well, but because of ring3 and interrupts I'm going to need one anyway I decided to just accept it.

I think some time ago I did not set TR to point to a valid TSS and everything worked just fine in ring0, so in that sense it wasn't needed, but I'm not sure if GRUB (or QEMU -kernel) had set it for me, can't remember if I even checked.

Kevin, from which version is that from? Couldn't find the same quote after quickly checking the 1986 version, or anything similar.. Might not have looked hard enough though..

LtG wrote:I think some time ago I did not set TR to point to a valid TSS and everything worked just fine in ring0, so in that sense it wasn't needed, but I'm not sure if GRUB (or QEMU -kernel) had set it for me, can't remember if I even checked.

I guess it works in practice, but if something in newer processors changes to require a valid TSS in additional places, and you code breaks, you get to keep both pieces and can't blame Intel.

Kevin, from which version is that from? Couldn't find the same quote after quickly checking the 1986 version, or anything similar.. Might not have looked hard enough though..

The copy in which I looked it up is from June 2009. If you don't target specifically a 80386 CPU, but also newer ones, you're probably better off not using ancient documentation.

I'm not suggesting not using a TSS since it's practically required (the mentioned interrupts and ring3 for example), was just curios myself if I could avoid it so thought I'd comment..

Btw, isn't all 32-bit x86 supposed to be backwards compatible with 80386, so Intel should not be making any changes that would break code not using TSS..

Also the osdev wiki doesn't mention anything about TSS in the protected mode:
http://wiki.osdev.org/Protected_Mode

Going without a TSS in ring 0 is safe, as long as you don't explicitly use one.

Nice,

Thanks