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share a bug: remember flush your TLB when writing page table

Posted: Mon Jul 13, 2015 6:39 am
by miaowei
I know many people will ignore this post when they see the title, because they know it. But I still post here, because i hope to help some one like me.
I have wasted over a week on a bug due to this.(Don't laugh at me)
At first, i thought bochs is not that clever to emulate TLB, but it does.
And I didn't pay much attention to TLB(I believe it's transparent), this is another cause .
and I also want to share my happiness with you now ^.^
(Beijing night 8:38)

Re: share a bug: remember flush your TLB when writing page t

Posted: Mon Jul 13, 2015 2:05 pm
by cds84
Yup...

And after flushing the TLB, depending on the architecture, you may also need to invalidate the data-cache, instruction cache, and branch predictor.
Maybe even flush the pipeline!

Re: share a bug: remember flush your TLB when writing page t

Posted: Mon Jul 13, 2015 9:31 pm
by Brendan
Hi,
miaowei wrote: I have wasted over a week on a bug due to this.(Don't laugh at me)
TLB invalidation bugs are nearly always "Heisenbugs" - random/confusing symptoms that are different on different hardware and disappear or change when you try to investigate; where it's painfully difficult to figure out the actual cause.

One week to find a bug like this isn't unusual at all.


Cheers,

Brendan