DMA status is 0 on qemu

[markq]

Hi,

I been trying to enable DMA on qemu. I have ran the device enumeration to find out that BAR4 is 0. This means that base address is 0 for the DMA bus master. However after checking status I get zero. I am not sure if this an error or I am using the wrong BAR4. Below is how I tried accessing the status:

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s1 = inb(0xa);
s2 = inb(0x0);

According to below table 0x2 and 0xa should be respective offset for status port:

byte offset function
(Primary ATA bus)
0x0 Command (byte)
0x2 Status (byte)
0x4-0x7 PRDT Address (uint32_t)
(Secondary ATA bus)
0x8 Command (byte)
0xA Status (byte)
0xC-0xF PRDT Address (uint32_t)

[madanra]

0 does not sound like a valid base address. I expect there is something wrong in your enumeration code. Have you tried dumping the whole config space to the screen to sanity check that the other fields make sense?

[markq]

0 does not sound like a valid base address. I expect there is something wrong in your enumeration code. Have you tried dumping the whole config space to the screen to sanity check that the other fields make sense?

I have used below code to enumerate all devices in configuration space. The value I got for device was:

0x1237
0x7000
0xb8
0x100e

vendor:
0x8086
0x8086
0x1013
0x8086

Command:
0x103
0x103
0x103
0x103

I believe that the command field is suppose to indicate whether there is a bus master on bit 2 (first is bit 0).

However, bit 2 is 0 so does that mean there is no bus master?

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uint16_t pciConfigReadWord(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) {
  uint32_t address;
  uint32_t lbus = (uint32_t)bus;
  uint32_t lslot = (uint32_t)slot;
  uint32_t lfunc = (uint32_t)func;
  uint16_t tmp = 0;
  
  address = (uint32_t)((lbus << 16) | (lslot << 11) |
		       (lfunc << 8) | (offset & 0xfc) | ((uint32_t)0x80000000));
  outl(0xCF8, address);
  tmp = (uint16_t)((inl (0xCFC) >> ((offset & 2) * 8)) & 0xffff);
  return tmp;

}

void kmain(mem_info *m_info, int n_entries) {
  clear_screen();
  init_descriptor_tables();
  init_physical_manager(m_info, n_entries);
  init_timer(50);

  asm volatile("sti");
  uint16_t r;
  uint16_t device_id;
  int bus, device;
  for (bus = 0; bus<256; bus++) {
    for (device = 0; device<32; device++) {
      r = pciConfigReadWord(bus, device,0,0);
      if (r != 0xffff) {
  	device_id  = pciConfigReadWord(bus, device,0,0x2);
  	kprintf("0x%x\n",device_id);
      }
    }
  }
}

[Combuster]

I suggest you start with reading the PCI page thoroughly. Your code is broken to the point where it misses the actual disk controller. (hint: it's at function > 0)

[markq]

I suggest you start with reading the PCI page thoroughly. Your code is broken to the point where it misses the actual disk controller. (hint: it's at function > 0)

I have added an extra for loop that loops through all possible function values (0 - 7), I was able to discover the below devices and parameters:

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bus 0 device 0 func 0  device_id: 0x1237 class/subclass: 0x600 cmd: 0x103
bus 0 device 1 func 0  device_id: 0x7000 class/subclass: 0x601 cmd: 0x103
bus 0 device 1 func 1  device_id: 0x7010 class/subclass: 0x101 cmd: 0x103
bus 0 device 1 func 3  device_id: 0x7113 class/subclass: 0x680 cmd: 0x103
bus 0 device 2 func 0  device_id: 0xb8   class/subclass: 0x300   cmd: 0x103
bus 0 device 3 func 0  device_id: 0x100e class/subclass: 0x200 cmd: 0x103

According to the link you provided, it says a class of 0x1 and subclass id of 0x20 should indicate the ATA controller (single DMA). However, the values above doesn't seem to have such values. Also the cmd values doesn't seem to indicate that a bus master exist...

[markq]

According to PCI database, device 0x7010 is a IDE controller. The header type of this device is 0x0. BAR4 is also 0xC041.

So I have tried extracting the actually address according to the PCI article. The value I got was 0x3010. Next, I tried reading the status but to no avail I get 0xff which I think isn't correct.