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Nable wrote:What can you tell about BAR4? Look at https://groups.google.com/forum/#!topic ... OHHHiHTNg4 , especially at the code that is posted there.

Nable wrote:Hm, does your PCI enumeration + BARs reading code work for any other devices?

Nable wrote:By the way, it looks like a good I/O port BAR at 0xC000, did you try to detect it's size and if its length is 16 - use it as a base port for ATA driver?
I've looked at my current laptop under Linux:

Code: Select all

$ lspci -v
...
00:1f.1 IDE interface: Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) IDE Controller (rev 03) (prog-if 8a [Master SecP PriP])
        Flags: bus master, medium devsel, latency 0, IRQ 16
        I/O ports at 01f0 [size=8]
        I/O ports at 03f4
        I/O ports at 0170 [size=8]
        I/O ports at 0374
        I/O ports at 1c00 [size=16]
        Kernel driver in use: ata_piix
...

lweb20 wrote:Still I am not sure how to use that port. I keep reading.

Nable wrote:

lweb20 wrote:Still I am not sure how to use that port. I keep reading.

Finding the further information seems to be an easy task: http://wiki.osdev.org/PCI_IDE_Controlle ... Controller -> it's a "Bus Master IDE" port base -> google://bus+mastering+site:wiki.osdev.org -> http://wiki.osdev.org/ATA/ATAPI_using_D ... r_Register

Hm, maybe presence of PCI_IDE_Controller article was a non-obvious thing. It looks like I've found it when some weeks ago I was reading random pages from OSDev Wiki.

lweb20 wrote:I get it. Must use the standard ports (legacy) in compatibility mode and native mode should use the ports in the BAR's. But what is the best way to detect these modes?

We hardcode the ISA ranges for BARs 0 through 3 if a PCI IDE controller has the "Primary" or "Secondary" bits set in its programming interface register and don't even look at the BARs. *code follows*

Nable wrote:

lweb20 wrote:I get it. Must use the standard ports (legacy) in compatibility mode and native mode should use the ports in the BAR's. But what is the best way to detect these modes?

Sorry, I don't know the best way but working way looks like this: if you have some "invalid" values (0 or 1) in BARs, then you have to try default ISA IDE ports, else you can try values from BARs.
Link from my first post in this topic suggests the following idea:

We hardcode the ISA ranges for BARs 0 through 3 if a PCI IDE controller has the "Primary" or "Secondary" bits set in its programming interface register and don't even look at the BARs. *code follows*

PCI Programming Interface Register (ICH Function 1 PCI Config. Offset 09h)

Primary Capabilities
0: Compatibility Only Supported
1: Native and Compatibility Supported

Secondary Capabilities
0: Compatibility Only Supported
1: Native and Compatibility Supported

The Primary/Secondary Capabilities indicators are “Read-Only” bits, where a “1”
indication is only available with ICH3.