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MIPSel barebones troubles

Posted: Wed Jun 25, 2014 1:02 pm
by habs
Hello all; I'm trying to build a simple OS for my mips64el netbook (Lemote Yeeloong) using the target triplet "mipsel-elf". With a little help from CFE Bare Bones, Dominic Sweetman's See MIPS Run, my CPU datasheet, and my GPU datasheet, I conjured up a mipsel-elf cross-compiler toolchain in /usr/local/cross and these files:

entry.s:

Code: Select all

.global start
.extern kernel_main

.set noreorder

.set STACKSIZE, 0x1000

.section .text

start:
	la $sp, stack
	addiu $sp, STACKSIZE - 32
	jal kernel_main
	nop
	b .
	nop

.section .bss
stack:
	.space STACKSIZE
main-minimal.c:

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#include <stdint.h>
#include <stddef.h>

void kernel_main()
{
	uint16_t* buffer = (uint16_t*) 0xB8000;
	for (size_t i = 0; i < 80*25; i++)
		buffer[i] = ((uint16_t) '&') | ((uint8_t) 7) << 8;
}
ldscript:

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OUTPUT_FORMAT(elf32-littlemips)
OUTPUT_ARCH(mips:isa32)
ENTRY(start)

SECTIONS
{
	.text (0xBFC0) :
	{
		*(.text)
		*(.text.*)
		*(.stub)
		*(.gnu.linkonce.t.*)
	}

	.rodata ALIGN(4K) :
	{
		*(.rodata*)
		*(.gnu.linkonce.r.*)
	}

	.data ALIGN(4K) :
	{
		*(.data*)
		*(.gnu.linkonce.d.*)
	}

	.bss ALIGN(4K) :
	{
		*(.common)
		*(.bss*)
		*(.gnu.linkonce.b.*)
	}

	/DISCARD/ :
	{
		*(.gcc_except_table)
		*(.eh_frame)
		*(.note)
		*(.comment)
		*(.rel.*)
		*(.rela.*)
	}
}
build.sh:

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#!/bin/bash
set -e
export PREFIX="/usr/local/cross"
export TARGET=mipsel-elf
export PATH="$PREFIX/bin:$PATH"
mipsel-elf-as -o entry.o entry.s -mfix-loongson2f-nop -mfix-loongson2f-jump
#mipsel-elf-gcc -o main.o -c main.c -std=c99 -Wall -Wextra -Werror -ffreestanding -nostdlib -fno-builtin -nostartfiles -nodefaultlibs -O2 -Wa,-mfix-loongson2f-nop,-mfix-loongson2f-jump
mipsel-elf-gcc -o main.o -c main-minimal.c -std=c99 -Wall -Wextra -Werror -ffreestanding -nostdlib -fno-builtin -nostartfiles -nodefaultlibs -O2 -Wa,-mfix-loongson2f-nop,-mfix-loongson2f-jump
mipsel-elf-ld -T ldscript -o kernel.elf entry.o main.o
#sudo mount /dev/sda1 /mnt/boot
#sudo cp kernel.elf /mnt/boot
#sudo umount /dev/sda1
I'd like to get it working in qemu-system-mipsel first and then try it on the real thing (only because rebooting is a bit of pain). My real goal here is to use as little asm as possible to get to C, then display something on the screen using VGA text mode (which is implemented by my GPU).

The problem is that when I run "qemu-system-mipsel -kernel kernel.elf", I just get a VGA blank mode screen (in other words, just blackness) instead of the screen being filled up with the '&' character as expected. If I had to guess where the problem was I would definitely say it's in the ldscript; I know very little about how linking works and it's entirely possible that 0xBFC0 is not what I should be putting there.

Brains of OSDev, do you have any advice for me? Does this code pass a sanity check? What would you reccommend to me for making this work?

Re: MIPSel barebones troubles

Posted: Thu Jun 26, 2014 2:55 am
by xenos
I don't know whether QEMU can simulate the type of laptop you have. By default qemu-system-mipsel simulates a Malta Core LV. According to this the ISA address space, and thus also the VGA memory, should be at 0x10000000, so for QEMU you should write to 0x100B8000 instead.

Re: MIPSel barebones troubles

Posted: Thu Jun 26, 2014 2:56 am
by Tuxality
I don't think you should write to 0xB8000 on MIPSel. You may need to recalculate the memory address. It might be 0xb0000000 + PHYSICAL_ADDRESS, but I may be wrong. Look at Linux-MIPS sources for reference if needed.

Re: MIPSel barebones troubles

Posted: Thu Jun 26, 2014 4:15 am
by embryo
habs wrote:Hello all; I'm trying to build a simple OS for my mips64el netbook (Lemote Yeeloong) using the target triplet "mipsel-elf". With a little help from CFE Bare Bones, Dominic Sweetman's See MIPS Run, my CPU datasheet, and my GPU datasheet
I don't know about the STLS family processors and can not help you, but you have pointed to the interesting processor architecture. I haven't read about it and as it seems after reading the Loongson2FUserGuide.pdf the STLS family processors are really cool chips. They allow a programmer to have very tight hardware control like direct SDRAM management, cache management, latency management and more. Really interesting processor! Nice to meet something closer to my "ideal" hardware picture than traditional x86.

Re: MIPSel barebones troubles

Posted: Thu Jun 26, 2014 3:03 pm
by xenos
Tuxality wrote:It might be 0xb0000000 + PHYSICAL_ADDRESS, but I may be wrong.
Indeed, it should be 0xb00b8000 here (not 0x100b8000 as I wrote before), since according to the QEMU docs the correct physical address for the ISA bus is 0x10000000 + ISA_ADDRESS, and these physical addresses can be accessed uncached via 0xa0000000 + PHYS_ADDRESS.