x86 sfence vs cache flush

[garyv]

Code example:

mov [mem], eax
sfence

After sfence instruction is executed, the data in eax is written to cache or memory?

If it's written to memory, "cache flush" operation is NOT needed. Right?

If it's written to cache, how to do cache flush on x86?

This question is very important when a processor load some code to mem then execute the code.

[Combuster]

This serializing operation guarantees that every store instruction that precedes in program order the SFENCE instruction is globally visible before any store instruction that follows the SFENCE instruction is globally visible

Since this is the x86 manual, globally here means the scope of hardware mentioned in the documents, i.e. all processors. It might be RAM, but it can just as well be the cache coherency mechanisms that make sure all CPUs read the expected answer.

This question is very important when a processor load some code to mem then execute the code.

If the processor loads the code, then it doesn't matter if it ends up in cache or in memory, because it will see it just as it put it there.