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I have decided to create a amd64 long mode based os from my beginning of a 32-bit os project, and my quetsion is related to the GDT/IDT.
For reference I have read over a reasonable amount of the AMD System Programmers Manual vol2.

In 32-bit pmode a 8 byte GDT would be used, now if i were to enable paging extentions and put the processor into long mode would it require modifications to the GDT or would it be able to accept it as usable?

I am thinking it might be able to use it allthough i have not tested this, any opinions facts on this matter are well apreciated ^^

I also wonder what changes will be required for the IDT list asside making the handler use 64-bit registers. Will i need 2 sets of IDT code perhaps?
One to install in long mode, and one for regular pmode?

edit: i realized i typed 6 instead of 8 above i have a really crappy monitor thats getting replaced soon.

edit: ok it seems i missed that part, it said the GDTR is 8 bytes in the amd manual, and its 6 bytes in legacy mode so basically i can just make a gdt_ptr struct with 2 entries one for limit one for base with 64-bit values and then load it with gdt_setgate_64, so to do this for my C code somthing to this effect.


struct gdt_entry_64 {
unsigned short limit_low; // 32 bit limit low
unsigned short base_low; // 32-bit base low
unsigned char base middle; // 32bit base low
unsigned char access; // 32 bit access flags
unsigned char granularity; //32-bit granularity flag
unsigned char base_high; //32-bit base high
unsigned char high_reserved1; // bits 32-63 low
unsigned char high_reserved2; // bits 32-63 high
} __attribute__((packed));


// the thing i find really funny is that they still use a 16 bit limit on a 64
// bit descriptor
struct gdt_ptr_64 {
unsigned short limit; // 16 bit limit
unsigned long base; // 64-bit base adress
}

Ok what i typed before probably looks really dumb, since i had the wrong idea bout it.
here is a snippet from the struct that i redid following figure 4.20 on page 109 in the amd 64 programmers manual vol 2 for Code Descriptor Long Mode.

struct gdt_entry_64
{ // Bits:
unsigned short limit_low; // 0-15 (limit 15-0)
unsigned short base_low; // 16-31 (base 15-0)
unsigned char base_middle; // 32-39 base middlle (16-23 of base)
unsigned char access; // 40-47 40=A,41=R,42=C,43=1,44=1,45-46=DPL, 47=P
unsigned char granularity; // 48-54 48-51=(segment limit 19-16), 52=AVL, 53=Long, 54=D, 55=Granularity
unsigned char base_high; // 63-55 (Base Adress 31-24)
// what about base adress 32-63?
} __attribute__((packed));

Ok so far so good but it just seems wierd, where is the rest of base adress? like 32-63 I am trying to understand how this works here. The book says that this is the structure for a long mode code segment -_-

Ok i have figured it out , i realized that when you switch to long mode, for the GDT code segment it doesnt matter if it has a 32-bit base adress anyhow, it is disabled, caus its greyed out thus theres no real need to store the extra bits of base adress when they are ignored anyways, the only difference between 32-bit GDT and 64-bit GDT is the fact taht one of the reserved bits now represents L, the long mode bit.

It seems i have answered my own question and hopefully somone finds this interesting ^^