Edge triggered line sharing
Posted: Thu Feb 13, 2014 9:45 am
Edge semantics mean a billion different things but this question is mostly based on pc/at x86 architecture using an ioapic. Not the isa 8259 or eisa pic.
This isn't something I plan to implement or do, it is a question based purely on curiosity.
Since the ioapic recognizes edges at a well defined point in time (bottom or top of it's clock), the datasheet says that subsequent edges will not be recognized or generate interrupt cycles until the target cpu(s) has accepted it onto it's IRR.
Theoretically speaking then, since we are still at the beginning of our interrupt service routine dispatch, we could still run the entire IRQ chain for that line. (like when 2 pci devices share a line, we run both routines to see who needs attention.)
This leads me to believe that some edge triggered devices, could possibly malfunction if their device registers are read when it really didn't assert it's line. Is that one of the reasons?
This isn't something I plan to implement or do, it is a question based purely on curiosity.
Since the ioapic recognizes edges at a well defined point in time (bottom or top of it's clock), the datasheet says that subsequent edges will not be recognized or generate interrupt cycles until the target cpu(s) has accepted it onto it's IRR.
Theoretically speaking then, since we are still at the beginning of our interrupt service routine dispatch, we could still run the entire IRQ chain for that line. (like when 2 pci devices share a line, we run both routines to see who needs attention.)
This leads me to believe that some edge triggered devices, could possibly malfunction if their device registers are read when it really didn't assert it's line. Is that one of the reasons?