OSDev.org

Hi,

does anyone have any idea what steps are required to survive clearing the IM bit in the LSU register on UltraSPARC II/IIi? The code is running from identity-mapped virtual memory and the membar #Synch instruction is issued after the write to that register.

When I run it in a simulator (Simics), everything is ok. However when the same piece of code is run on a real Ultra 5 with UltraSPARC IIi, it never makes it past the write to the LSU register. My guess is that a trap is received...

And yes, interrupts are disabled in the PSTATE register.

Thanks,
Jakub

Can't say that I'll be much help here, in fact most of us are x86 hackers. However I do have access to lots of Blade 100s, Blade 1000s, Utlra 60s, and even a Ultra 10(but that's not really different then an Ultra 5). If you need some testing done that won't take hours I can probably help out(current workload permitting).