I have a question regarding tlb flush IPI delay.
As Brendan concluded:
<quote>
To summarise, each time you modify the paging structures (page table/s, page directory/s, etc), you'd:
- invalidate the TLB on the current CPU
- determine if the stale TLB entry could be used in an "unsafe" way:
- if "no", then other CPUs can rely on their page fault handlers to invalidate the TLB entries and you don't need to do anything else
- if "yes", then determine if any other CPUs could be effected by the change:
- if "yes", then send an IPI to any/all other CPUs that could be effected, to ensure they invalidate their TLB too
- if "no" (e.g. page belongs to a single-threaded process that can't be running on any other CPU) then you don't have to do anything else
if any target CPUs will be effected by the change, before the IPI arrives late, if the target CPU is running.
Is it possible that it will access the stale TLB entry which has been modified by the sender.