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I have read this section (intel volume3 8.6) for a whole evening, it says

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The CPUID feature flag may indicate support for hardware multi-threading when only one logical processor avail-
able in the package. In this case, the decimal value represented by bits 16 through 23 in the EBX register will have
a value of 1.
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I am confused about "The CPUID feature flag', what does it mean? refer in particular to "Hardware Multi-Threading feature flag",or just means the feature of 1(or some) bit in regiester returned by instruction 'cpuid'? Here is the context:

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8.6
DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY
Use the CPUID instruction to detect the presence of hardware multi-threading support in a physical processor.
Hardware multi-threading can support several varieties of multigrade and/or Intel Hyper-Threading Technology.
CPUID instruction provides several sets of parameter information to aid software enumerating topology informa-
tion. The relevant topology enumeration parameters provided by CPUID include:
• Hardware Multi-Threading feature flag (CPUID.1:EDX[28] = 1) — Indicates when set that the physical
package is capable of supporting Intel Hyper-Threading Technology and/or multiple cores.
• Processor topology enumeration parameters for 8-bit APIC ID:
— Addressable IDs for Logical processors in the same Package (CPUID.1:EBX[23:16]) — Indicates
the maximum number of addressable ID for logical processors in a physical package. Within a physical
package, there may be addressable IDs that are not occupied by any logical processors. This parameter
does not represents the hardware capability of the physical processor.5
• Addressable IDs for processor cores in the same Package6 (CPUID.(EAX=4, ECX=07):EAX[31:26] +
1 = Y) — Indicates the maximum number of addressable IDs attributable to processor cores (Y) in the physical
package.
• Extended Processor Topology Enumeration parameters for 32-bit APIC ID: Intel 64 processors
supporting CPUID leaf 0BH will assign unique APIC IDs to each logical processor in the system. CPUID leaf 0BH
reports the 32-bit APIC ID and provide topology enumeration parameters. See CPUID instruction reference
pages in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
The CPUID feature flag may indicate support for hardware multi-threading when only one logical processor avail-
able in the package. In this case, the dec
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Hi,

miaowei wrote:I am confused about "The CPUID feature flag', what does it mean? refer in particular to "Hardware Multi-Threading feature flag",or just means the feature of 1(or some) bit in regiester returned by instruction 'cpuid'?

They mean the "HTT feature flag". Basically what they're saying is:

If the CPU supports hyper-threading then the "HTT flag" (bit 28 returned in EDX by CPUID leaf 0x00000001) will be set. A CPU may support hyper-threading but only have one logical CPU per core (which is very similar to not supporting hyper-threading at all). In that case the "HTT flag" will be set, and the number of logical CPUs in the core will be 1.


Cheers,

Brendan

Brendan wrote: A CPU may support hyper-threading but only have one logical CPU per core (which is very similar to not supporting hyper-threading at all).

Thanks!
I know what you mean, but my mind is alittle chaos for another sentence(also in this section that i showed above):
"Within a physical package, there may be addressable IDs that are not occupied by any logical processors."
According to this secntence, if i were cpuid, i can return an arbitary value larger than the existed logiclal processor num when you call me with leaf 4., because "there may be addressable IDs that are not occupied by any logical poocessors", because i don't need to return you the real logic-processors value. isn't it? If so, what is the sense in that?

Hi,

miaowei wrote:I know what you mean, but my mind is alittle chaos for another sentence(also in this section that i showed above):
"Within a physical package, there may be addressable IDs that are not occupied by any logical processors."
According to this secntence, if i were cpuid, i can return an arbitary value larger than the existed logiclal processor num when you call me with leaf 4., because "there may be addressable IDs that are not occupied by any logical poocessors", because i don't need to return you the real logic-processors value. isn't it? If so, what is the sense in that?

That's correct - for example, you could have a CPU that reserves 8 APIC IDs but only has 2 logical CPUs.

There's a few reasons for this. First; Intel tend to make the same CPU and then disable cores and other things (cache, virtualisation, etc) to convert those same CPUs into different models. For example, they might make a batch of 4-core CPUs with hyper-threading and find out (during testing) that for 10% of them there's a problem with one of the cores and then disable 2 of the cores on those CPUs so that they can sell them as a 2-core CPU instead of throwing them away. In this case the chip might be designed to reserve 8 APIC IDs, but for the 2-core model half of those APIC IDs can't/won't be used.

Second; on some systems hyper-threading may be disabled by firmware. For example, you might have a 2-core CPU with hyper-threading that reserves 8 APIC IDs (where only 4 APIC IDs could be used), where the user tells the firmware to disable hyper-threading and only 2 APIC IDs are seen by the OS.

Also note that APIC IDs are assigned by hardware during power-on (and not assigned by software after power-on) and therefore you can't really expect to have a complex "APIC ID allocator" that avoids ending up with gaps of unused APIC IDs.


Cheers,

Brendan