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This bit field in an IOAPIC INTIN entry indicates that the relevant interrupt is level triggered and has already been sent out on the bus and accepted by the target APIC.

At first I thought maybe this bit could be used to indicate to software (in the case of a shared IRQ line) after it cleared the hardware source of a level triggered interrupt, that another one is already being asserted.

But if that were the case, then the relevant APIC would already have its IRR set.

So to make my question more clear, I'm looking for the general purpose of remote IRR and further, why EOI cycles clear it.

damn I guess no one uses it

I had a few theories though, partly confirmed by the ioapic spec.

Since edges on the input line can be missed, the ioapic only ignores them if the target lapic's IRR is already set when the interrupt message is sent out on the apic bus.

Since level triggered is just holding the line until the relevant software for the device clears it, i'm thinking that the ioapic just saves cycles and does not bother checking till an EOI cycle from a lapic clears the relevant remote IRR.

this is probably obvious to some of you, but I was trying to develop a nice mental map of it's protocols.