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In long mode when you load CR8 with the priority class, TPR bits 0-3 are cleared, but intel docs seem a little fuzzy to me on whether or not bits 0-3 of a vector mean anything towards actual interrupt servicing.

Say I have a class of interrupts with a TPR[7:4] priority of 2, and lets say TPR[3:0] is zero.

Then lets say I get an interrupt on cpu0 being vector 48 (decimal). This is interrupt priority class 3, sub class 0.

My question is, can this ISR then be preempted by any ISR to this same cpu that has the same priority class of 3, but then a sub class of 1? even though our PPR is held at 3 for the duration of the ISR until we change it?


thanks

Hi,

As far as I know...

For Intel CPUs only; there's:

• an 8-bit TPR (Task Priority Register) that you can set directly (e.g. like any other local APIC register)
• CR8 which is aliased to bits 4 to 7 of the TPR, which can't be used to read TPR bits 0 to 3 and can't be used to set TPR bits 0 to 3 to anything other than zero
• An internal 8-bit PPR (Processor Priority Register) which determines if IRQs are sent to the CPU or postponed
• An internal 8-bit APR (Arbitration Priority Register) which is used for "send to lowest priority" delivery to determine which CPU receives the IRQ

If the TPR's class is higher priority than the in service interrupt's class, then all 8 bits of the PPR contains all 8 bits of the TPR, and all 8 bits of the APR contains all 8 bits of the TPR. However, the lowest 4 bits of the PPR don't seem to effect anything anyway.

If the TPR's class is lower priority than the in service interrupt's class, then the PPR contains "ISRV & 0xF0" and the APR contains "ISRV & 0xF0".

If the TPR's class is equal to the in service interrupt's class, then the PPR is model specific (lowest 4 bits of PPR may contain zero or whatever is in the TPR's lowest 4 bits), and for the APR it depends on the sub-class values (zero if ISRV subclass is higher priority and equal to the TPRs lowest 4 bits otherwise).

For AMD's CPUs; AMD treat the entire local APIC as "model specific" and may have slightly different rules to determine the values for PPR and APR. I don't know what these rules are (it's a pain in the neck to find out as it's scattered across different documents for different model CPUs). They may use Intel's rules for all AMD CPUs, but they could use different rules (e.g. always ignore the lowest 4 bits of everything) for all AMD CPUs, or different AMD CPUs may do different things.

devsau wrote:Say I have a class of interrupts with a TPR[7:4] priority of 2, and lets say TPR[3:0] is zero.

Then lets say I get an interrupt on cpu0 being vector 48 (decimal). This is interrupt priority class 3, sub class 0.

My question is, can this ISR then be preempted by any ISR to this same cpu that has the same priority class of 3, but then a sub class of 1? even though our PPR is held at 3 for the duration of the ISR until we change it?

In this case PPR will be 0x30 and only interrupts 0x40 or higher will be able to interrupt, because the processor priority class determines the priority threshold for interrupting (which is only the highest 4 bits and not all 8 bits of the PPR) and because only interrupts 0x40 (with priority class of 4 or more) have a priority class higher than 3.

In a similar way, if you set TPR to 0x33 then only interrupts 0x40 and higher will be able to interrupt, and interrupt 0x3F can't interrupt (because 3 is not higher than 3) even though 0x3F is higher than 0x33.

Basically; (I think) the only case where the lowest 4 bits of the TPR, PPR or APR matter is for lowest priority delivery mode; where the lowest 4 bits of TPR can effect APR and can effect which CPU is lower priority (and which CPU receives the interrupt).


Cheers,

Brendan

Thanks Brendan for the help as always.

I was just confused cause intel seems to hint/indicate when it explains the vector sub class:

low 4 bits indicating its ranking within the interrupt-priority class.

just left me confused after reading the paragraphs that follow in the manual. I read it over like 15 times

thank you

Sorry to bump this, but it leads me to another question. In my long mode kernel, i set the TPR with cr8 (which also sets ppr) and effectively clears the low 4 bits of both (the sub-class).

I do this in an ISR before i return to the interrupted instruction (obviously with interrupts masked until iret).

So lets say additional IRR bits are set within the same priority level (PPR 7:4) and this happens while interrupts are masked, so they are pending. When our routine returns and interrupts are enabled, they are accepted into the ISR in sub-priority order?

edited for clarity