Looking for some clarity on the Message Address Register
Posted: Mon Sep 23, 2013 4:48 pm
Lets say on a particular machine i'm routing a certain frequency comparator(hpet) to the FSB instead of ioapic/8259.
The following is from the intel manuals:
The following is from the intel manuals:
further:Destination ID — This field contains an 8-bit destination ID. It identifies the message’s target processor(s).
The destination ID corresponds to bits 63:56 of the I/O APIC Redirection Table Entry if the IOAPIC is used to
dispatch the interrupt to the processor(s).
3. Redirection hint indication (RH) — This bit indicates whether the message should be directed to the
processor with the lowest interrupt priority among processors that can receive the interrupt.
• When RH is 0, the interrupt is directed to the processor listed in the Destination ID field.
• When RH is 1 and the physical destination mode is used, the Destination ID field must not be set to
0xFF; it must point to a processor that is present and enabled to receive the interrupt.
• When RH is 1 and the logical destination mode is active in a system using a flat addressing model, the
Destination ID field must be set so that bits set to 1 identify processors that are present and enabled to
receive the interrupt.
• If RH is set to 1 and the logical destination mode is active in a system using cluster addressing model,
then Destination ID field must not be set to 0xFF;
I bolded what I am a little confused about. In particular I want to know about RH being zero, is the destination ID then the apic id? or the logical apic id?If RH is 0, then the DM bit is ignored and the message is sent ahead independent of whether the physical or
logical destination mode is used.
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