IOAPIC and IOMMU interrupt remapping
Posted: Mon Sep 16, 2013 9:01 am
Hi Folks,
I'm trying to figure out the path of an interrupt, from it's device to the destination CPU when IOMMU is enabled. I've read through many discussions but found very few talking about the interaction between IOAPIC and IOMMU. To know this, I need to know the physical topology of these chips (IOMMU's interrupt remapping table and I/O APIC).
So I first start with dumping information from my Linux kernel 3.6 with Xeon E3-1230v2 CPU. AFAIK, for Xeon, the I/O APIC is located in the southbridge chipset (Intel C204, also known as PCH, platform controller hub), so every device from the southbridge will go through
[Device Pin-based Interrupt] --> [IOAPIC's routing entry] --> [IOMMU remapping entry] -->[CPU].
http://en.wikipedia.org/wiki/Platform_Controller_Hub
However, two PCIex16 buses are directly connected to the northbridge, which is integrated into the Xeon CPU now in the Intel Sandy bridge architecture. In this case, it makes no sense that interrupts still go to the IOAPIC at southbridge. (Is it correct?) So I assume for these PCIex16 devices, the legacy pin-based interrupt is NOT supported, only the MSI-X is working. The MSI-X interrupt path should be
[Device's MSI-X Interrupt] --> [IOMMU remapping entry index] --> [CPU]
So I guess for MSI-X, there is no longer IOAPIC is involved in the path of interrupts, is it correct?
The I/O APIC is only there for supporting the pin-based interrupts, and for MSI-X, since the address/data says everything about routing, there is no need to go through the IOAPIC.
Regards,
Cheng-Chun Tu (Stony Brook University)
I'm trying to figure out the path of an interrupt, from it's device to the destination CPU when IOMMU is enabled. I've read through many discussions but found very few talking about the interaction between IOAPIC and IOMMU. To know this, I need to know the physical topology of these chips (IOMMU's interrupt remapping table and I/O APIC).
So I first start with dumping information from my Linux kernel 3.6 with Xeon E3-1230v2 CPU. AFAIK, for Xeon, the I/O APIC is located in the southbridge chipset (Intel C204, also known as PCH, platform controller hub), so every device from the southbridge will go through
[Device Pin-based Interrupt] --> [IOAPIC's routing entry] --> [IOMMU remapping entry] -->[CPU].
http://en.wikipedia.org/wiki/Platform_Controller_Hub
However, two PCIex16 buses are directly connected to the northbridge, which is integrated into the Xeon CPU now in the Intel Sandy bridge architecture. In this case, it makes no sense that interrupts still go to the IOAPIC at southbridge. (Is it correct?) So I assume for these PCIex16 devices, the legacy pin-based interrupt is NOT supported, only the MSI-X is working. The MSI-X interrupt path should be
[Device's MSI-X Interrupt] --> [IOMMU remapping entry index] --> [CPU]
So I guess for MSI-X, there is no longer IOAPIC is involved in the path of interrupts, is it correct?
The I/O APIC is only there for supporting the pin-based interrupts, and for MSI-X, since the address/data says everything about routing, there is no need to go through the IOAPIC.
Regards,
Cheng-Chun Tu (Stony Brook University)