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I decided that if cpuid indicates that TSC is 'invariant' (frequency of counter does not fluctuate between acpi power states) that I will use it as the perf counter for user-level operations.

In the Intel manual they also recommend this, but their claim is that it would 'reduce overhead' from the other option being a platform clock like an HPET.

My question is why exactly would they expect there to be more overhead? If assuming paging is enabled and the hardware registers are mapped as un-cacheable... is that the reasoning?

Anyone want to shed some light on their ideas or what you do in your own OS ?

thanks

devsau wrote:their claim is that it would 'reduce overhead' from the other option being a platform clock like an HPET.

Reading the TSC is an instruction of the processor. Reading an external clock requires a kernel call or a security hole.