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I double checked the IOAPIC specification to see if I missed it, in case I did.. maybe someone can enlighten me. My current setup is that interrupts from all peripherals other then the timing chip are set to lowest priority in their corresponding IOAPIC field. My box has 4 logical cores so with the LDR mask configured accordingly, it will interrupt the processor running at the lowest priority (I use long mode.. so cr8=0).

The question is, what happens if, for a time, all logical cores are at the same level when an interrupt is ready? Is it held and then sent to whichever local apic goes to a lower priority level first?

Hi,

doxrobot wrote:The question is, what happens if, for a time, all logical cores are at the same level when an interrupt is ready? Is it held and then sent to whichever local apic goes to a lower priority level first?

It's CPU/chipset specific; but as far as I know usually the IRQs just goes to the "first" CPU if all CPUs are at the same priority. It's never held waiting for a CPU's priority to change, as this may never happen (e.g. think of an idle computer).


Cheers,

Brendan