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Hi all,

I'm trying to simulate pages smaller than 4KB on an x86. Basically I want the page fault handler to run each time someone accesses within a 1KB area. With the 4KB pages, I can get a page fault every 4KB. Is there some way to simulate 2KB pages in any way? Could this be simulated by invalidating the page and having the fault handler run every read? This would probably take up a lot of cycles and I was wondering if there are any creative ways to do this without incurring this cost. Perhaps anything with segment registers?

Thanks!

Hi,

What's the bigger picture with what you are trying to achieve? Perhaps there's a better way of handling whatever problem you are trying to solve than by using 2KiB pages?

Cheers,
Adam

Hi,

h311b0y wrote:I'm trying to simulate pages smaller than 4KB on an x86. Basically I want the page fault handler to run each time someone accesses within a 1KB area. With the 4KB pages, I can get a page fault every 4KB. Is there some way to simulate 2KB pages in any way? Could this be simulated by invalidating the page and having the fault handler run every read? This would probably take up a lot of cycles and I was wondering if there are any creative ways to do this without incurring this cost. Perhaps anything with segment registers?

The main problem will be correctly handling things that cross "artificial page boundaries". For example, consider this instruction:
In this case, "foo" might not be aligned and might write 2 bytes in one 2 KiB page and another 2 bytes in another 2 KiB page. In the same way, the instruction itself may be split across 2 artificial pages, and the stack may be misaligned too. This means that a single instruction may access 6 different pages. There is no way to handle these "accesses split on artificial page boundaries" with paging, segmentation, or both.

One way this can be done is by emulating the CPU in software (e.g. like Bochs). This would take a lot of work and will be slow.

To attempt to speed it up you might be able to invent some complex/tricky scheme where most instructions run natively and only some instructions are emulated. For example, pages could be set to "not present" where the page fault handler makes them "present" again, and then the alignment check exception could be used to ensure that an access to a "temporarily present" page doesn't effect multiple artificial pages. Then (afterwards) you'd need to make the page "not present" again, and could use the "single-step" debugging exception for that. In this case, you'd only have to emulate instructions in the alignment check exception handler. However; it'd be even more work and would still be extremely slow (due to massive numbers of exceptions - maybe an average of 1 exceptions per instruction if you're lucky); and emulating all instructions may be faster.

The "least slow" method would be JIT, where you convert small pieces of "code that needs to be emulated" into small pieces of native code and (e.g.) replace memory accesses with function calls that handle the reads/writes. This is also likely to be the most complex method (especially for 80x86 code, which is a lot messier than something like Java byte-code that was designed for JIT).

Mostly; AJ is right - it's better to figure out why you think you want to do this and find a more practical solution that doesn't involve simulating smaller page sizes.

EDIT: Also note that simulating larger page sizes is quite easy - e.g. if you wanted to use 16 KiB pages for some reason.


Cheers,

Brendan

if there are just 2 Pages with 2 KB, you could align them on the middle between 2 pages.
so you have a page from 0x1000 to 0x2000 and another Page from 0x2000 to 0x3000
you could set the pointer to 0x1800.
from 0x1800 to 0x1FFF it would be 2 KB in Page1 and from 0x2000 to 0x27FF it would be another 2 KB in Page 2.

Maybe is there some Debug register you can use...

What do you want to use this for?