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cianfa72 wrote:So these newer architectures (e.g. Sandy Bridge) share the same logical view of the older ones ? (based on processor + MCH chipsets)

cianfa72 wrote:IIUC the Host Bridge/DRAM controller (bus 0 device 0 function 0) from a logical point of view acts as an initiator/target PCI interface on "virtual PCI bus 0" side (initiator or bus master when it has to forward CPU access to PCI memory mapped devices, target or slave when PCI bus mastering devices initiate a DMA in system RAM).

Now I expect to find BARs entries used to decode DMA access to main RAM (i.e. when HostBridge/DRAM controller acts as a bus 0 PCI target)...but I do not see them...

cianfa72 wrote:Now in my mind a piece is missing: accesses coming from DMI interface (initiated by a DMA bus mastering device) how are managed by the DRAM controller ? Does exist specific registers for that ?

     ___________
    |           |
    | CPU cores |
    |___________|
         |
     ____|______________      _________________
    |                   |    |                 |
    | Memory Controller |----| DRAM Controller |--- DRAM chip/s
    |___________________|    |_________________|
           |
     ______|______________
    |                     |
    | PCI Host Controller |
    |_____________________|
           |
     ______|_____
    |            |
    | PCI Bus/es |--- PCI devices
    |____________|

cianfa72 wrote:But in the case of IOMMU (as you said inserted between PCI host controller and Memory Controller) the mangling is performed only in upstream direction (from bus mastering PCI device initiating DMA accesses towards system RAM) ?

cianfa72 wrote:From Intel specs of my chipset (see the link above) the "Uncore" include a Device 0, a multifunction Device 1 and a Device 2 (IGD: Integrated Graphic Device). Now coming back to your diagram I believe that:

Device 0 implement the first two "things" (Memory controller + DRAM controller) + Host/PCI bridge (using a "pretend device's PCI configuration space");
Device 1's functions implement "virtual PCI-PCI" bridges (Are these the PCI Host controllers did you refer to in this thread ?)

• Bus 0, device 0, function 0 = Memory controller and DRAM controller
  Bus 0, device 1, functions 0 to 2 = PCI host bridges (probably connected to PCI slots on motherboard)
  Bus 0, device 6, functions 0 = PCI host bridge (probably used internally for onboard video only)
  Bus X, device 2, function 0 = onboard video (I'd assume bus is determined by corresponding host bridge "secondary bus" register)

cianfa72 wrote:second: from specs it seem "positive decoding" is involved in decoding memory ranges either to DRAM or PCI (I thought all ranges decoded to PCI or DMI should be only "subtractively decoded")

if( (address > start1) && (address < end1) ) {
    // Positively decoded, send to "somewhere1"
} else if( (address > start2) && (address < end2) ) {
    // Positively decoded, send to "somewhere2"
} else {
    // Subtractively decoded, send to "somewhere3"
}

Brendan wrote: To me it looks like:

• Bus 0, device 0, function 0 = Memory controller and DRAM controller
  Bus 0, device 1, functions 0 to 2 = PCI host bridges (probably connected to PCI slots on motherboard)
  Bus 0, device 6, functions 0 = PCI host bridge (probably used internally for onboard video only)
  Bus X, device 2, function 0 = onboard video (I'd assume bus is determined by corresponding host bridge "secondary bus" register)

cianfa72 wrote:

Brendan wrote: To me it looks like:

• Bus 0, device 0, function 0 = Memory controller and DRAM controller
  Bus 0, device 1, functions 0 to 2 = PCI host bridges (probably connected to PCI slots on motherboard)
  Bus 0, device 6, functions 0 = PCI host bridge (probably used internally for onboard video only)
  Bus X, device 2, function 0 = onboard video (I'd assume bus is determined by corresponding host bridge "secondary bus" register)

quoting Intel specs

"2.4 Processor Register Introduction
The processor contains two sets of software accessible registers, accessed using the Host processor I/O address space — Control registers and internal configuration registers

• Control registers are I/O mapped into the processor I/O space, which control access to PCI and PCI Express configuration space (see Section 2.4.1)

• Internal configuration registers residing within the processor are partitioned into three logical device register sets (“logical” since they reside within a single physical device). The first register set is dedicated to Host Bridge functionality (that is, DRAM configuration, other chipset operating parameters and optional features). The second register block is dedicated to Host-PCI Express Bridge functions (controls PCI Express interface configurations and operating parameters). The third register block is for the internal graphics functions"

So (Memory controller + DRAM controller) device should be the "Host Bridge" device in Intel description...

cianfa72 wrote:As final point, as you can see, onboard video - IGD (Device 2 function 0) resides on bus 0 (it has not attached behind a PCI bridge on a secondary bus)

I can see "power on" default values, but I can't see what the firmware would set any of these registers to during boot. For example; for all of the "Host-PCI Express Bridge" the secondary bus number is 0 (until the firmware sets it to something sane). I mostly just assumed that one of those "Host-PCI Express Bridge" would be used for the inbuilt graphics, and that the inbuilt graphics was "bus 0" because that's the power on default (and not because it's sane).

Also note that I have been ignoring your "!pci" dumps because I don't know what this utility is or if it's reliable, and because the information it displays doesn't correspond to things documented in the datasheet. For example, "bus 0, device 1, function 1" isn't mentioned in any of them. This tells me that either the "!pci" utility is dodgy or the hardware is not what the datasheet describes.

lkd> !pci 100 0 0 0
PCI Configuration Space (Segment:0000 Bus:00 Device:00 Function:00)
Common Header:
    00: VendorID       8086 Intel Corporation
    02: DeviceID       0104
    04: Command        0006 MemSpaceEn BusInitiate 
    06: Status         2090 CapList FB2BCapable InitiatorAbort 
    08: RevisionID     09
    09: ProgIF         00
    0a: SubClass       00 Host Bridge
    0b: BaseClass      06 Bridge Device
    0c: CacheLineSize  0000
    0d: LatencyTimer   00
    0e: HeaderType     00
    0f: BIST           00
   ............
Device Private:
    40: fed19001 00000000 fed10001 00000000
    50: 00000211 00000019 af90000f ab000001
    .......