Why CCC(Command Completion Coalescing) test failed ?

[liaoo]

Dear all,
I have one question about the testing of AHCI's CCC(Command Completion Coalescing) function...

According to AHCI spec v1.3, chapter 11:

Command Completion Coalescing (CCC) is a feature designed to reduce the interrupt and command completion overhead in a heavily loaded system. The feature enables the number of interrupts taken per completion to be reduced significantly, while ensuring a minimum quality of service for command completions.

After reading the doc I setup a testing scenario:

• 1. Disable CCC_CTL.EN first(to update CCC_CTL.CC field)

• 2. Set CCC_PORTS = 0x00000001, indicating Port0 is part of the CCC feature

• 3. Set CCC_CTL.CC = 5, indicating the number of command completions that are necessary to cause a CCC interrupt

• 4. Set CCC_CTL.EN = 1 to enable this feature

• 5. Issue 5 FPDMA Write Queued commands to device and observe the IS.IPS(32bits)

* Assume CCC_CTL.INT = 6, indicating when CCC interrupt occurs IS.IPS[6] will be 1

My expected results will be:

• Issue 1st command to device...

• After command complete IS.IPS[6] = 0

• Issue 2nd command to device...

• After command complete IS.IPS[6] = 0

• Issue 3rd command to device...

• After command complete IS.IPS[6] = 0

• Issue 4th command to device...

• After command complete IS.IPS[6] = 0

• Issue 5th command to device...

• After command complete IS.IPS[6] = 1

But I found IS.IPS[6] = 1 immediately after 1st command is completed...!

I want to know if this scenario is correct or not

[liaoo]

I found the reason why CCC interrupt generated immediately after 1st command completed in this scenario:

11.4 Interrupt Definition
The command coalescing completion interrupt, called the ‘CCC interrupt’, is generated on any of the following conditions:
• hCccComplete is greater than or equal to the value specified by software in CCC_CTL.CC and CCC_CTL.CC != 0
• hCccTimer is decremented to 0h. (The interrupt is generated on the decrement to 0h, not the decrement from 0h to -1.)
• hCccComplete is incremented and there are no more commands outstanding on the selected ports for command completion coalescing and CCC_CTL.CC != 0.

In my scenario software issues command one by one thus there is only 1 bit is "1" in PxCI[] !

[liaoo]

Dear all,
I have one question about below initializations when activating CCC feature:

11.6 Software Behavior
To initialize use of the command completion coalescing feature for a set of ports, software needs to
perform several steps.
1. Software should turn off per port interrupts for the D2H Register FIS and the Set Device Bits FIS
(clear PxIE.DHRE and PxIE.SDBE to ‘0’) for each port that will be part of command completion
coalescing.
2. Software should turn on per port interrupts for hot plug and error events. These events should be
handled on a per port basis.

Why should software clear these 2 bits before enabling CCC feature ?

[liaoo]

I found if these 2 bits are enabled, then there are more interrupts generated and this violates the spirit of CCC. Besides PxIE.DPE should be disabled, too.