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According to AHCI spec, software can initiate interface power management state transitions if the link layer is currently in the L_IDLE state. After reading involved document I summarize the steps as below trying to put the interface into the Partial state.

• - issue read/write commands to device first

• - after commands completed while loop to check if PxCMD.ICC = 0 or not

• (... wait until PxCMD.ICC = 0 and this means the HBA is ready to to accept a new interface command...)

• - set PxCMD.ICC = 2(2 indicates "Partial" state)

• - wait for PxCMD.ICC back to "0" (spec said HBA will update this back to idle finally...)

• - while loop to check if PxSSTS.IPM = 2 (where 2 means: current interface is in Partial state)

The result was: PxSSTS != 2 for a long time and I guess the interface did not enter the partial state...

* In this configuration CAP.SSC = PSC = 1 and I set PxSCTL.IPM = 0(no interface restrictions)

My question is: Do I check if device support this interface power management state transition in this case ?

Thanks !

I found below descriptions in sata spec:

Word 76: Serial ATA capabilities
...
Bit 9 when set to one indicates that the Serial ATA device supports the Partial and Slumber
interface power management states when initiated by the host. Devices shall support either host
initiated interface power management or device-initiated interface power management. If word 78
bit 3 is cleared to zero, then word 77 bit 9 shall be set to one

And I found this bit is 0 for the testing drive. After using the other drive with that bit = 1 entering Partial or Slumber state is OK.

Can I conclude that this bit decides if drive support these state transitions ?