IDE controller: IO space, 400 ns delay

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arkady
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IDE controller: IO space, 400 ns delay

Post by arkady »

I've been trying to figure out how hard disks work (from software point of view). Now the time has come for easier stuff like IDE. I have a few questions on the subject and of general nature.

1. IDE controller is a PCI device. Some use legacy IO addresses (like 0x1f0), others use different sets (native mode). Not more than 10 IO addresses are used (for Command Block Registers & Control Block Registers). Is it possible to use memory-mapped IO instead? I know that would be a total waste but is it possible? Can IDE controller respond to IO port space OR memory-mapped IO? Is it all about programming BARs?

2. When reading Wiki articles about ATA and IDE (http://wiki.osdev.org/ATA_PIO_Mode) I noticed they both mention that 400 ns delays are needed when reading status register. Similar statements can be found in ATA\ATAPI specs. OK, fine. But it is interesting how Wiki suggests this delay can be achieved (quote): "read the Status register FIVE TIMES, and only pay attention to the value returned by the last one -- after selecting a new master or slave device. The point being that you can assume an IO port read takes approximately 100ns, so doing the first four creates a 400ns delay". My question is why 1 input instruction from alternate status register takes roughly 100 ns? Is it CPU independent? Or maybe IN timing is dependent on device being "queried"? I only found timing for IN instruction on 486 CPU - not more than 30 cycles. For a 2GHz CPU (2,000,000,000 ticks/s - one tick every 0,5 ns) even 100 cycles would be a lot less than 100 ns for one IN instruction. What am I missing here?
cyr1x
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Re: IDE controller: IO space, 400 ns delay

Post by cyr1x »

@2: The instruction itself actually is pretty fast, but the CPU has a WAIT-input (or similar), which a device may pull for a longer period of time.
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bewing
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Re: IDE controller: IO space, 400 ns delay

Post by bewing »

Stated another way, the IO Port bus is an 8-bit BUS attached to the CPU, and all buses have their own timing -- independent of the CPU. The timing of the bus has to be slow enough to accomodate the slowest device on that bus.
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