Message Signaled Interrupt support in DOS...

[liaoo]

Hi all,

I am working on testing the MSI feature of PCI card in "DOS" mode and I have some questions...

(1) How to configure the "Message Address Register" in the capability ?
Ex. Destination ID ?
Ex. Redirection hint ?
Ex. Destination Mode ?

* In my environment(DOS) I think I can set them to:
Destination ID = 0 ( equal to "local APIC ID" in 0xFEE00020 )
RH = 0 (interrupt is directed to processor listed in the Destination ID field)
Destination Mode = x(ignored according to IA SW Developer's manual Vol 3)

(2) How to configure the "Message Data Register" in the capability ?

* I guess I have to retrieve all interrupt vectors and found an "empty" one then assign to it ? Am I right ?

(3) Do I need to enable IO/APIC ?

* I think "no need to enable IO/APIC" because MSI will be translated to interrupt message request by chipset then present on FSB... Am I right ?

(4) How do I "allocate" the vector for my service routine ?

Could anyone give me some directions about these questions ?

Thanks in advance...

[rdos]

You don't need to enable IO-APIC in order to use MSI. MSI sends the message directly to the CPU (APIC), much like the IO-APIC probably also does. But you need to enable the local APIC in order for this to work. Which interrupt vector to use is up to you.

[liaoo]

[Q] How to check if local APIC is enabled ?

* I found below way to check and ......is it correct ?
- locate IA32_APIC_BASE MSR => at MSR 01Bh
- use RDMSR then check "APIC global/disable bit" (bit11)

Then I got "FEE00900" and it indicates:
- APIC global enable (due to bit11 = 1)
- Processor is BSP (due to bit8 = 1)
- APIC base [35:12] = 0xFEE000

[Q] Another question will be: to allocate the vector, I have to access the IO-APIC registers, right ?

[rdos]

[Q] How to check if local APIC is enabled ?

* I found below way to check and ......is it correct ?
- locate IA32_APIC_BASE MSR => at MSR 01Bh
- use RDMSR then check "APIC global/disable bit" (bit11)

Then I got "FEE00900" and it indicates:
- APIC global enable (due to bit11 = 1)
- Processor is BSP (due to bit8 = 1)
- APIC base [35:12] = 0xFEE000

[Q] Another question will be: to allocate the vector, I have to access the IO-APIC registers, right ?

The vector is part of the MSI data (if I don't remember it wrong). Look at the APIC section in the Intel docs, which has a rudimentary description of MSI as well.

[liaoo]

I found the vector in http://wiki.xomb.org/index.php?title=I/ ... Controller

Vector - The vector that is used to deliver the interrupt on the actual core. Valid values range from 0x10 to 0xFE

Assume I set the vector to 0x10, then what does 0x10 mean

* I guess the processor gets this value than calculates to obtain the "entry point" of interrupt service routine... (the reason why I asked is I do not know where I can put my own service routine and how to do it )

[liaoo]

I made a summary of what I should(might) do to support MSI in DOS mode as below:

• 1.decide MME based on MMC in the MSI capability registers(in my case MME can be 0 for Single MSI is used)

• 2.config Address and Data registers in the MSI capability registers

• 3.setup IO-APIC registers - IOREDTBL[x] for this interrupt

• 4.install my own interrupt service routine for that vector Ex. vector = 0x10

• 5.Enable MSI by setting MC.MSIE = 1(disable PIC mode)

Do I miss something ?

Besides I want to know how to install self-defined routine for this MSI, does anyone give some suggestions ?

[liaoo]

I list what I have done as below and maybe you all can help to clarify these...

(1) Multiple Message Enable = 0( for single MSI set this field = 0; MMC = 100b)

(2) For MSI message address
- bit[31:20] = 0xFEE
- bit[19:12] = 0 (Destination ID)
- bit3 = 0 (Redirection hint = 0)
- bit2 = 0 (Destination Mode, don't care because of RH = 0)

(3) For MSI message data
- bit15 = 0 (trigger mode = edge)
- bit14 = 0 (trigger level, ignored if trigger mode = edge)
- bit[10:8] = 000 (delivery mode = fixed)
- bit[7:0] = 0x20 (vector, and I choose to use 0x20)

(4) Finally enable MSI by setting MSICAP.MC.MSIE = 1

@ I have roughly read the doc(chapter 10) http://download.intel.com/products/proc ... 253668.pdf
@ I think there is no need to program IO APIC and Local APIC registers because MSI does not route to APIC system...!

Current status: I found system hang after enabling MSIE = 1 and device generates interrupt via MSI !

Note: In above sequence the service routine is NOT installed because I have no idea how to do it...( is this the reason why my app hang ? )

[liaoo]

When setting the vector in Message Data field to 0x20, app hang...But if set to 0x76, I found app did not hang and then I can check if device generates interrupt and Local APIC receives this interrupt message as below:

#1. For PCI device(AHCI controller):

• a) ID(Interrupt Disable) = 0

• b) IS(Interrupt Status) = 0

• c) MSI Cap = 09,FEE00000,00000076

#2 For AHCI HBA registers:

• a) PxIS = 00000023

• b) PxIE = 7DC0007F

• c) IS = 00000001

• d) IE bit1 = 1

By #1 and #2 I think device successfully sends the message to request service because:

• 1. IS bit0 = 1(Port 0 has pending interrupt status)

• 2. IE(Interrupt Enable) = 1

• 3. PCI Command register bit10(ID) = 0

• 4. MSICAP.MC.MSIE = 1(to MSI engine)

Also I found the LAPIC receives this interrupt message because:

• 1. Local APIC IRR(Interrupt Request Register) bit118(=0x76) = 1

• 2. Local APIC ISR(In-Service register) bit118(=0x76) = 1

Thus it seems that device generates the interrupt and Local receives this; even so, my service routine is NOT called

The other thing I am interested is:
@ During the operation this PCI device "totally" sends 3 messages to request service(3 bits set in PxIS) and this means 3 messages with the same interrupt vector(0x76) are sent to the processor.

@ I found both ISR bit118 and IRR bit118 = 1. This means when 1st interrupt is being served 2nd interrupt is coming and received by LAPC...

Can LAPIC queue "requests" ?

[liaoo]

After setting the vector to 0x70 and installing the ISR by DPMI calls 0x204/205 now my own service routine is successfully invoked

But I still don't know why app failed with vectors 0x20 and 0x76 ? (but OK with vector 0x70... )