Moving to PAE-paging
Posted: Fri Aug 17, 2012 2:11 pm
I searched the current code-base for dependency on page-table structures. Essentially, all of these are referenced with 4 selectors, 2 for the system page tables and 2 for the current process page tables. One selector is for the page directory, and one is for the page tables. It turns out that a large majority of the references are to the process page table selector (in total about 70 references), and those are in many modules, including some device-drivers. The other 3 selectors are only referenced in a few relevant kernel modules.
An additional problem is that the API to manipulate physical memory should be changed to use 64-bits (two 32-bit registers, like EBX:EAX). There are about 150 references to these functions. Some of these allocations must return a physical address below 4G, while most can handle any address (page table manipulations).
I think a good idea is to provide new functions to manipulate the process page table selector (and thus phase-out the direct usage of process page table). Then I would provide new physical memory manipulation functions and migrate to them. After this is done, it is fairly easy to just change a few functions in order to switch to PAE mode. And best of all, if the CPU doesn't support PAE, it works seemlessly with typical paging as well.
But which mappings would long mode / PAE use? Long mode uses 4 levels of page tables, so does that mean 4 mappings would be created (page tables, page dir, directory ptr and PML4)? The full page-table alias for 48-bit addresses would use too much memory (512G if I've calculated it correctly), so that would not be possible. The 32-bit code would probably only map the first 4G in 3 mappings. (page tables, page dir, and 4bit of directory pointer). The full mappings would require long mode to access.
An additional problem is that the API to manipulate physical memory should be changed to use 64-bits (two 32-bit registers, like EBX:EAX). There are about 150 references to these functions. Some of these allocations must return a physical address below 4G, while most can handle any address (page table manipulations).
I think a good idea is to provide new functions to manipulate the process page table selector (and thus phase-out the direct usage of process page table). Then I would provide new physical memory manipulation functions and migrate to them. After this is done, it is fairly easy to just change a few functions in order to switch to PAE mode. And best of all, if the CPU doesn't support PAE, it works seemlessly with typical paging as well.
But which mappings would long mode / PAE use? Long mode uses 4 levels of page tables, so does that mean 4 mappings would be created (page tables, page dir, directory ptr and PML4)? The full page-table alias for 48-bit addresses would use too much memory (512G if I've calculated it correctly), so that would not be possible. The 32-bit code would probably only map the first 4G in 3 mappings. (page tables, page dir, and 4bit of directory pointer). The full mappings would require long mode to access.