clear APIC IRR

[dschatz]

I'm trying to poll interrupts. I can detect that an interrupt has come in on the IRR by reading it. I could service the interrupt right there without enabling interrupts in CFLAGS. However, I couldn't find a way to clear bits from the IRR. Is there any way to do this or am I going about this the wrong way?

[FallenAvatar]

Why are you polling? o.O

[Nable]

Use EOI (End-Of-Interrupt) registers to acknowledge serviced interrupt, Luke.

[dschatz]

EOI only acks the ISR, not the IRR according to the intel manual. Can you point me to documentation that says otherwise?

Polling is nice because I only take interrupts at explicit points in time, so I would rather just call the corresponding handler than take an interrupt which causes a pipeline flush and other slowdown.

[Combuster]

Then don't check the PIC, but rather the device itself you're interested in.

[dschatz]

The issue is that it could be a number of devices. I think explicitly checking every potential interrupt generating device in the system doesn't scale.

[gerryg400]

The issue is that it could be a number of devices. I think explicitly checking every potential interrupt generating device in the system doesn't scale.

Do you think it's possible that interrupts are provided for that reason ?

[dschatz]

The issue is that it could be a number of devices. I think explicitly checking every potential interrupt generating device in the system doesn't scale.

Do you think it's possible that interrupts are provided for that reason ?

First of all there are plenty of reasons why interrupts are provided that have nothing to do with the scalability of polling. Second of all, I'm asking how to clear the IRR on the APIC, not how to check every interrupt generating device in the system. I just want to know how I can poll for interrupts without talking to every device in the system. If its not possible or no one knows, thats fine.

[gerryg400]

The issue is that it could be a number of devices. I think explicitly checking every potential interrupt generating device in the system doesn't scale.

Do you think it's possible that interrupts are provided for that reason ?

First of all there are plenty of reasons why interrupts are provided that have nothing to do with the scalability of polling. Second of all, I'm asking how to clear the IRR on the APIC, not how to check every interrupt generating device in the system. I just want to know how I can poll for interrupts without talking to every device in the system. If its not possible or no one knows, thats fine.

Wait a minute. It was you that complained about having to explicitly check every interrupt generating device. And it was you that complained about it not scaling.

Anyway to answer your original question, you cannot write to the IRR. An EOI will clear the highest set ISR bit potentially making way for bit in the IRR to be transferred to the ISR. Bits in the IRR are not explicitly cleared, they are moved to the ISR. Let's say that IRR bit 100 is set. That bit will not be cleared (moved to ISR 100) until every bit of higher priority in the ISR is cleared by EOI.

I've not tried this with polling but I can't immediately see why it won't work.

[Combuster]

ISR means in-service-register. To get a bit into the ISR, you need to accept an interrupt.