MIPS32 exception handling

[mete]

Hello everyone.
I'm trying to get exception handling running on a MIPS32R2 CPU. To be specific a Broadcom BCM5356 SoC on some cheap wifi router.

Whenever I'm triggering an exception(tried with: syscall instruction, division through 0 or UART interrupt) the system freezes. It doesn't seem to jump to the exception handler, and it doesn't execute the instructions after the one that caused the exception.
Right now all the assembler exception handler does is writing 'c' characters to the UART in an infinite loop for testing purposes, but I don't receive any of them(if I call the exception handler manually I see the expected output, so that should work).

I'm testing on real hardware and debugging through serial/UART output.

What my kernel is doing so far is:

• - Setting up the stack
  - Jumping to C code where I have a tiny printf() implementation outputting text over the UART
  - clear the CP0 Status and Cause registers
  - memcpy() the exception handler to the general exception handler address, which should be 0x80000180(also tried 0x8000000 and 0x80000200)
  - trigger exception with either:
  • * syscall instruction. system freezes
    * division by 0. when I trigger with div by 0, sometimes I receive an infinite stream of 'a' characters. I have double checked and verified that nowhere in my code I'm sending these characters, and I don't know where they're coming from.
    * enabling the IE bit and the IM bit corresponding to the UART in CP0_STATUS and triggering an UART interrupt. system freezes
  - print some text on the UART to check if the system is still alive, which I never receive

Also I'm trying to use the "Compatibility Mode" for exception handling, as the MIPS32 manual calls it. I don't want to/haven't tried to use any of the vectored interrupt features the R2 offers. I verified that the BEV bit in CP0_STATUS and IV bit in CP0_CAUSE are both 0, which should bring me into compatibility mode with the general exception handler located at 0x80000180.

I read the Exception handling parts in the MIPS32 manual Volume 3 and can't find anything that I might be doing wrong. Any hints are very much appreciated!

- Thomas

[mete]

Here's an update, it seems to work now.
The CPU jumps to the exception handler if I write the exception handler using uncached memory access. So instead of writing the handler to 0x80000180, I write it to 0xA0000180 in KSEG1, which is the same address in physical memory, but circumventing the CPU's cache.
I realized this after the CPU started jumping to the exception handler after I accidentally accessed around 32kb of RAM after writing the handler to 0x80000180, but before triggering the exception. As the CPU's cache is only 32kb it had to write the exception handler to real memory.

I still wonder why the CPU doesn't jump to the exception handler if it's only in the cache, and I couldn't find anything about it in the MIPS32 docs. There is a cache error exception handler, which is explicitly accessed through KSEG1 memory, implying that the general exception handler should work cached.

I'm glad it works reliably now, but if anyone has any insights about this cache issue, I'm happy to hear it.

Thomas

[xenos]

I'm not a MIPS expert, but IIRC you need to sync the I- and D-caches between the memcpy of your code to the exception handler address and raising an exception (provided that you have enabled caches, but I assume that this is the case).

[mete]

That makes sense I guess. I didn't think of the separate caches, but having to synchronize them seems plausible. I will do some research about that topic.

Thanks for your help